1 /* 2 * Driver for the TWSI (i2c) controller found on the Marvell 3 * orion5x and kirkwood SoC families. 4 * 5 * Author: Albert Aribaud <albert.u.boot@aribaud.net> 6 * Copyright (c) 2010 Albert Aribaud. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <asm/io.h> 15 16 /* 17 * include a file that will provide CONFIG_I2C_MVTWSI_BASE 18 * and possibly other settings 19 */ 20 21 #if defined(CONFIG_ORION5X) 22 #include <asm/arch/orion5x.h> 23 #elif defined(CONFIG_KIRKWOOD) 24 #include <asm/arch/kirkwood.h> 25 #else 26 #error Driver mvtwsi not supported by SoC or board 27 #endif 28 29 /* 30 * TWSI register structure 31 */ 32 33 struct mvtwsi_registers { 34 u32 slave_address; 35 u32 data; 36 u32 control; 37 union { 38 u32 status; /* when reading */ 39 u32 baudrate; /* when writing */ 40 }; 41 u32 xtnd_slave_addr; 42 u32 reserved[2]; 43 u32 soft_reset; 44 }; 45 46 /* 47 * Control register fields 48 */ 49 50 #define MVTWSI_CONTROL_ACK 0x00000004 51 #define MVTWSI_CONTROL_IFLG 0x00000008 52 #define MVTWSI_CONTROL_STOP 0x00000010 53 #define MVTWSI_CONTROL_START 0x00000020 54 #define MVTWSI_CONTROL_TWSIEN 0x00000040 55 #define MVTWSI_CONTROL_INTEN 0x00000080 56 57 /* 58 * Status register values -- only those expected in normal master 59 * operation on non-10-bit-address devices; whatever status we don't 60 * expect in nominal conditions (bus errors, arbitration losses, 61 * missing ACKs...) we just pass back to the caller as an error 62 * code. 63 */ 64 65 #define MVTWSI_STATUS_START 0x08 66 #define MVTWSI_STATUS_REPEATED_START 0x10 67 #define MVTWSI_STATUS_ADDR_W_ACK 0x18 68 #define MVTWSI_STATUS_DATA_W_ACK 0x28 69 #define MVTWSI_STATUS_ADDR_R_ACK 0x40 70 #define MVTWSI_STATUS_ADDR_R_NAK 0x48 71 #define MVTWSI_STATUS_DATA_R_ACK 0x50 72 #define MVTWSI_STATUS_DATA_R_NAK 0x58 73 #define MVTWSI_STATUS_IDLE 0xF8 74 75 /* 76 * The single instance of the controller we'll be dealing with 77 */ 78 79 static struct mvtwsi_registers *twsi = 80 (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE; 81 82 /* 83 * Returned statuses are 0 for success and nonzero otherwise. 84 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. 85 * Thus to ease debugging, the return status contains some debug info: 86 * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'. 87 * - bits 23..16 are the last value of the control register. 88 * - bits 15..8 are the last value of the status register. 89 * - bits 7..0 are the expected value of the status register. 90 */ 91 92 #define MVTWSI_ERROR_WRONG_STATUS 0x01 93 #define MVTWSI_ERROR_TIMEOUT 0x02 94 95 #define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \ 96 ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF)) 97 98 /* 99 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, 100 * return 0 (ok) or return 'wrong status'. 101 */ 102 static int twsi_wait(int expected_status) 103 { 104 int control, status; 105 int timeout = 1000; 106 107 do { 108 control = readl(&twsi->control); 109 if (control & MVTWSI_CONTROL_IFLG) { 110 status = readl(&twsi->status); 111 if (status == expected_status) 112 return 0; 113 else 114 return MVTWSI_ERROR( 115 MVTWSI_ERROR_WRONG_STATUS, 116 control, status, expected_status); 117 } 118 udelay(10); /* one clock cycle at 100 kHz */ 119 } while (timeout--); 120 status = readl(&twsi->status); 121 return MVTWSI_ERROR( 122 MVTWSI_ERROR_TIMEOUT, control, status, expected_status); 123 } 124 125 /* 126 * These flags are ORed to any write to the control register 127 * They allow global setting of TWSIEN and ACK. 128 * By default none are set. 129 * twsi_start() sets TWSIEN (in case the controller was disabled) 130 * twsi_recv() sets ACK or resets it depending on expected status. 131 */ 132 static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; 133 134 /* 135 * Assert the START condition, either in a single I2C transaction 136 * or inside back-to-back ones (repeated starts). 137 */ 138 static int twsi_start(int expected_status) 139 { 140 /* globally set TWSIEN in case it was not */ 141 twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; 142 /* assert START */ 143 writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control); 144 /* wait for controller to process START */ 145 return twsi_wait(expected_status); 146 } 147 148 /* 149 * Send a byte (i2c address or data). 150 */ 151 static int twsi_send(u8 byte, int expected_status) 152 { 153 /* put byte in data register for sending */ 154 writel(byte, &twsi->data); 155 /* clear any pending interrupt -- that'll cause sending */ 156 writel(twsi_control_flags, &twsi->control); 157 /* wait for controller to receive byte and check ACK */ 158 return twsi_wait(expected_status); 159 } 160 161 /* 162 * Receive a byte. 163 * Global mvtwsi_control_flags variable says if we should ack or nak. 164 */ 165 static int twsi_recv(u8 *byte) 166 { 167 int expected_status, status; 168 169 /* compute expected status based on ACK bit in global control flags */ 170 if (twsi_control_flags & MVTWSI_CONTROL_ACK) 171 expected_status = MVTWSI_STATUS_DATA_R_ACK; 172 else 173 expected_status = MVTWSI_STATUS_DATA_R_NAK; 174 /* acknowledge *previous state* and launch receive */ 175 writel(twsi_control_flags, &twsi->control); 176 /* wait for controller to receive byte and assert ACK or NAK */ 177 status = twsi_wait(expected_status); 178 /* if we did receive expected byte then store it */ 179 if (status == 0) 180 *byte = readl(&twsi->data); 181 /* return status */ 182 return status; 183 } 184 185 /* 186 * Assert the STOP condition. 187 * This is also used to force the bus back in idle (SDA=SCL=1). 188 */ 189 static int twsi_stop(int status) 190 { 191 int control, stop_status; 192 int timeout = 1000; 193 194 /* assert STOP */ 195 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; 196 writel(control, &twsi->control); 197 /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ 198 do { 199 stop_status = readl(&twsi->status); 200 if (stop_status == MVTWSI_STATUS_IDLE) 201 break; 202 udelay(10); /* one clock cycle at 100 kHz */ 203 } while (timeout--); 204 control = readl(&twsi->control); 205 if (stop_status != MVTWSI_STATUS_IDLE) 206 if (status == 0) 207 status = MVTWSI_ERROR( 208 MVTWSI_ERROR_TIMEOUT, 209 control, status, MVTWSI_STATUS_IDLE); 210 return status; 211 } 212 213 /* 214 * Ugly formula to convert m and n values to a frequency comes from 215 * TWSI specifications 216 */ 217 218 #define TWSI_FREQUENCY(m, n) \ 219 (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n))) 220 221 /* 222 * Reset controller. 223 * Called at end of i2c_init unsuccessful i2c transactions. 224 * Controller reset also resets the baud rate and slave address, so 225 * re-establish them. 226 */ 227 static void twsi_reset(u8 baud_rate, u8 slave_address) 228 { 229 /* ensure controller will be enabled by any twsi*() function */ 230 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; 231 /* reset controller */ 232 writel(0, &twsi->soft_reset); 233 /* wait 2 ms -- this is what the Marvell LSP does */ 234 udelay(20000); 235 /* set baud rate */ 236 writel(baud_rate, &twsi->baudrate); 237 /* set slave address even though we don't use it */ 238 writel(slave_address, &twsi->slave_address); 239 writel(0, &twsi->xtnd_slave_addr); 240 /* assert STOP but don't care for the result */ 241 (void) twsi_stop(0); 242 } 243 244 /* 245 * I2C init called by cmd_i2c when doing 'i2c reset'. 246 * Sets baud to the highest possible value not exceeding requested one. 247 */ 248 void i2c_init(int requested_speed, int slaveadd) 249 { 250 int tmp_speed, highest_speed, n, m; 251 int baud = 0x44; /* baudrate at controller reset */ 252 253 /* use actual speed to collect progressively higher values */ 254 highest_speed = 0; 255 /* compute m, n setting for highest speed not above requested speed */ 256 for (n = 0; n < 8; n++) { 257 for (m = 0; m < 16; m++) { 258 tmp_speed = TWSI_FREQUENCY(m, n); 259 if ((tmp_speed <= requested_speed) 260 && (tmp_speed > highest_speed)) { 261 highest_speed = tmp_speed; 262 baud = (m << 3) | n; 263 } 264 } 265 } 266 /* reset controller */ 267 twsi_reset(baud, slaveadd); 268 } 269 270 /* 271 * Begin I2C transaction with expected start status, at given address. 272 * Common to i2c_probe, i2c_read and i2c_write. 273 * Expected address status will derive from direction bit (bit 0) in addr. 274 */ 275 static int i2c_begin(int expected_start_status, u8 addr) 276 { 277 int status, expected_addr_status; 278 279 /* compute expected address status from direction bit in addr */ 280 if (addr & 1) /* reading */ 281 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; 282 else /* writing */ 283 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; 284 /* assert START */ 285 status = twsi_start(expected_start_status); 286 /* send out the address if the start went well */ 287 if (status == 0) 288 status = twsi_send(addr, expected_addr_status); 289 /* return ok or status of first failure to caller */ 290 return status; 291 } 292 293 /* 294 * I2C probe called by cmd_i2c when doing 'i2c probe'. 295 * Begin read, nak data byte, end. 296 */ 297 int i2c_probe(uchar chip) 298 { 299 u8 dummy_byte; 300 int status; 301 302 /* begin i2c read */ 303 status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1); 304 /* dummy read was accepted: receive byte but NAK it. */ 305 if (status == 0) 306 status = twsi_recv(&dummy_byte); 307 /* Stop transaction */ 308 twsi_stop(0); 309 /* return 0 or status of first failure */ 310 return status; 311 } 312 313 /* 314 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c 315 * Begin write, send address byte(s), begin read, receive data bytes, end. 316 * 317 * NOTE: some EEPROMS want a stop right before the second start, while 318 * some will choke if it is there. Deciding which we should do is eeprom 319 * stuff, not i2c, but at the moment the APIs won't let us put it in 320 * cmd_eeprom, so we have to choose here, and for the moment that'll be 321 * a repeated start without a preceding stop. 322 */ 323 int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 324 { 325 int status; 326 327 /* begin i2c write to send the address bytes */ 328 status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); 329 /* send addr bytes */ 330 while ((status == 0) && alen--) 331 status = twsi_send(addr >> (8*alen), 332 MVTWSI_STATUS_DATA_W_ACK); 333 /* begin i2c read to receive eeprom data bytes */ 334 if (status == 0) 335 status = i2c_begin( 336 MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1); 337 /* prepare ACK if at least one byte must be received */ 338 if (length > 0) 339 twsi_control_flags |= MVTWSI_CONTROL_ACK; 340 /* now receive actual bytes */ 341 while ((status == 0) && length--) { 342 /* reset NAK if we if no more to read now */ 343 if (length == 0) 344 twsi_control_flags &= ~MVTWSI_CONTROL_ACK; 345 /* read current byte */ 346 status = twsi_recv(data++); 347 } 348 /* Stop transaction */ 349 status = twsi_stop(status); 350 /* return 0 or status of first failure */ 351 return status; 352 } 353 354 /* 355 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c 356 * Begin write, send address byte(s), send data bytes, end. 357 */ 358 int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 359 { 360 int status; 361 362 /* begin i2c write to send the eeprom adress bytes then data bytes */ 363 status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); 364 /* send addr bytes */ 365 while ((status == 0) && alen--) 366 status = twsi_send(addr >> (8*alen), 367 MVTWSI_STATUS_DATA_W_ACK); 368 /* send data bytes */ 369 while ((status == 0) && (length-- > 0)) 370 status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK); 371 /* Stop transaction */ 372 status = twsi_stop(status); 373 /* return 0 or status of first failure */ 374 return status; 375 } 376 377 /* 378 * Bus set routine: we only support bus 0. 379 */ 380 int i2c_set_bus_num(unsigned int bus) 381 { 382 if (bus > 0) { 383 return -1; 384 } 385 return 0; 386 } 387 388 /* 389 * Bus get routine: hard-return bus 0. 390 */ 391 unsigned int i2c_get_bus_num(void) 392 { 393 return 0; 394 } 395