1 /* 2 * Driver for the TWSI (i2c) controller found on the Marvell 3 * orion5x and kirkwood SoC families. 4 * 5 * Author: Albert Aribaud <albert.u.boot@aribaud.net> 6 * Copyright (c) 2010 Albert Aribaud. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <linux/errno.h> 14 #include <asm/io.h> 15 #include <linux/compat.h> 16 #ifdef CONFIG_DM_I2C 17 #include <dm.h> 18 #endif 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* 23 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other 24 * settings 25 */ 26 27 #ifndef CONFIG_DM_I2C 28 #if defined(CONFIG_ORION5X) 29 #include <asm/arch/orion5x.h> 30 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) 31 #include <asm/arch/soc.h> 32 #elif defined(CONFIG_ARCH_SUNXI) 33 #include <asm/arch/i2c.h> 34 #else 35 #error Driver mvtwsi not supported by SoC or board 36 #endif 37 #endif /* CONFIG_DM_I2C */ 38 39 /* 40 * TWSI register structure 41 */ 42 43 #ifdef CONFIG_ARCH_SUNXI 44 45 struct mvtwsi_registers { 46 u32 slave_address; 47 u32 xtnd_slave_addr; 48 u32 data; 49 u32 control; 50 u32 status; 51 u32 baudrate; 52 u32 soft_reset; 53 }; 54 55 #else 56 57 struct mvtwsi_registers { 58 u32 slave_address; 59 u32 data; 60 u32 control; 61 union { 62 u32 status; /* When reading */ 63 u32 baudrate; /* When writing */ 64 }; 65 u32 xtnd_slave_addr; 66 u32 reserved[2]; 67 u32 soft_reset; 68 }; 69 70 #endif 71 72 #ifdef CONFIG_DM_I2C 73 struct mvtwsi_i2c_dev { 74 /* TWSI Register base for the device */ 75 struct mvtwsi_registers *base; 76 /* Number of the device (determined from cell-index property) */ 77 int index; 78 /* The I2C slave address for the device */ 79 u8 slaveadd; 80 /* The configured I2C speed in Hz */ 81 uint speed; 82 /* The current length of a clock period (depending on speed) */ 83 uint tick; 84 }; 85 #endif /* CONFIG_DM_I2C */ 86 87 /* 88 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control 89 * register 90 */ 91 enum mvtwsi_ctrl_register_fields { 92 /* Acknowledge bit */ 93 MVTWSI_CONTROL_ACK = 0x00000004, 94 /* Interrupt flag */ 95 MVTWSI_CONTROL_IFLG = 0x00000008, 96 /* Stop bit */ 97 MVTWSI_CONTROL_STOP = 0x00000010, 98 /* Start bit */ 99 MVTWSI_CONTROL_START = 0x00000020, 100 /* I2C enable */ 101 MVTWSI_CONTROL_TWSIEN = 0x00000040, 102 /* Interrupt enable */ 103 MVTWSI_CONTROL_INTEN = 0x00000080, 104 }; 105 106 /* 107 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1; 108 * on other platforms, it is a normal r/w bit, which is cleared by writing 0. 109 */ 110 111 #ifdef CONFIG_SUNXI_GEN_SUN6I 112 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 113 #else 114 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 115 #endif 116 117 /* 118 * enum mvstwsi_status_values - Possible values of I2C controller's status 119 * register 120 * 121 * Only those statuses expected in normal master operation on 122 * non-10-bit-address devices are specified. 123 * 124 * Every status that's unexpected during normal operation (bus errors, 125 * arbitration losses, missing ACKs...) is passed back to the caller as an error 126 * code. 127 */ 128 enum mvstwsi_status_values { 129 /* START condition transmitted */ 130 MVTWSI_STATUS_START = 0x08, 131 /* Repeated START condition transmitted */ 132 MVTWSI_STATUS_REPEATED_START = 0x10, 133 /* Address + write bit transmitted, ACK received */ 134 MVTWSI_STATUS_ADDR_W_ACK = 0x18, 135 /* Data transmitted, ACK received */ 136 MVTWSI_STATUS_DATA_W_ACK = 0x28, 137 /* Address + read bit transmitted, ACK received */ 138 MVTWSI_STATUS_ADDR_R_ACK = 0x40, 139 /* Address + read bit transmitted, ACK not received */ 140 MVTWSI_STATUS_ADDR_R_NAK = 0x48, 141 /* Data received, ACK transmitted */ 142 MVTWSI_STATUS_DATA_R_ACK = 0x50, 143 /* Data received, ACK not transmitted */ 144 MVTWSI_STATUS_DATA_R_NAK = 0x58, 145 /* No relevant status */ 146 MVTWSI_STATUS_IDLE = 0xF8, 147 }; 148 149 /* 150 * enum mvstwsi_ack_flags - Determine whether a read byte should be 151 * acknowledged or not. 152 */ 153 enum mvtwsi_ack_flags { 154 /* Send NAK after received byte */ 155 MVTWSI_READ_NAK = 0, 156 /* Send ACK after received byte */ 157 MVTWSI_READ_ACK = 1, 158 }; 159 160 /* 161 * calc_tick() - Calculate the duration of a clock cycle from the I2C speed 162 * 163 * @speed: The speed in Hz to calculate the clock cycle duration for. 164 * @return The duration of a clock cycle in ns. 165 */ 166 inline uint calc_tick(uint speed) 167 { 168 /* One tick = the duration of a period at the specified speed in ns (we 169 * add 100 ns to be on the safe side) */ 170 return (1000000000u / speed) + 100; 171 } 172 173 #ifndef CONFIG_DM_I2C 174 175 /* 176 * twsi_get_base() - Get controller register base for specified adapter 177 * 178 * @adap: Adapter to get the register base for. 179 * @return Register base for the specified adapter. 180 */ 181 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) 182 { 183 switch (adap->hwadapnr) { 184 #ifdef CONFIG_I2C_MVTWSI_BASE0 185 case 0: 186 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; 187 #endif 188 #ifdef CONFIG_I2C_MVTWSI_BASE1 189 case 1: 190 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; 191 #endif 192 #ifdef CONFIG_I2C_MVTWSI_BASE2 193 case 2: 194 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2; 195 #endif 196 #ifdef CONFIG_I2C_MVTWSI_BASE3 197 case 3: 198 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3; 199 #endif 200 #ifdef CONFIG_I2C_MVTWSI_BASE4 201 case 4: 202 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4; 203 #endif 204 #ifdef CONFIG_I2C_MVTWSI_BASE5 205 case 5: 206 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5; 207 #endif 208 default: 209 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); 210 break; 211 } 212 213 return NULL; 214 } 215 #endif 216 217 /* 218 * enum mvtwsi_error_class - types of I2C errors 219 */ 220 enum mvtwsi_error_class { 221 /* The controller returned a different status than expected */ 222 MVTWSI_ERROR_WRONG_STATUS = 0x01, 223 /* The controller timed out */ 224 MVTWSI_ERROR_TIMEOUT = 0x02, 225 }; 226 227 /* 228 * mvtwsi_error() - Build I2C return code from error information 229 * 230 * For debugging purposes, this function packs some information of an occurred 231 * error into a return code. These error codes are returned from I2C API 232 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.). 233 * 234 * @ec: The error class of the error (enum mvtwsi_error_class). 235 * @lc: The last value of the control register. 236 * @ls: The last value of the status register. 237 * @es: The expected value of the status register. 238 * @return The generated error code. 239 */ 240 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es) 241 { 242 return ((ec << 24) & 0xFF000000) 243 | ((lc << 16) & 0x00FF0000) 244 | ((ls << 8) & 0x0000FF00) 245 | (es & 0xFF); 246 } 247 248 /* 249 * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out. 250 * 251 * @return Zero if status is as expected, or a non-zero code if either a time 252 * out occurred, or the status was not the expected one. 253 */ 254 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, 255 uint tick) 256 { 257 int control, status; 258 int timeout = 1000; 259 260 do { 261 control = readl(&twsi->control); 262 if (control & MVTWSI_CONTROL_IFLG) { 263 status = readl(&twsi->status); 264 if (status == expected_status) 265 return 0; 266 else 267 return mvtwsi_error( 268 MVTWSI_ERROR_WRONG_STATUS, 269 control, status, expected_status); 270 } 271 ndelay(tick); /* One clock cycle */ 272 } while (timeout--); 273 status = readl(&twsi->status); 274 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, 275 expected_status); 276 } 277 278 /* 279 * twsi_start() - Assert a START condition on the bus. 280 * 281 * This function is used in both single I2C transactions and inside 282 * back-to-back transactions (repeated starts). 283 * 284 * @twsi: The MVTWSI register structure to use. 285 * @expected_status: The I2C bus status expected to be asserted after the 286 * operation completion. 287 * @tick: The duration of a clock cycle at the current I2C speed. 288 * @return Zero if status is as expected, or a non-zero code if either a time 289 * out occurred or the status was not the expected one. 290 */ 291 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status, 292 uint tick) 293 { 294 /* Assert START */ 295 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START | 296 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 297 /* Wait for controller to process START */ 298 return twsi_wait(twsi, expected_status, tick); 299 } 300 301 /* 302 * twsi_send() - Send a byte on the I2C bus. 303 * 304 * The byte may be part of an address byte or data. 305 * 306 * @twsi: The MVTWSI register structure to use. 307 * @byte: The byte to send. 308 * @expected_status: The I2C bus status expected to be asserted after the 309 * operation completion. 310 * @tick: The duration of a clock cycle at the current I2C speed. 311 * @return Zero if status is as expected, or a non-zero code if either a time 312 * out occurred or the status was not the expected one. 313 */ 314 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte, 315 int expected_status, uint tick) 316 { 317 /* Write byte to data register for sending */ 318 writel(byte, &twsi->data); 319 /* Clear any pending interrupt -- that will cause sending */ 320 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG, 321 &twsi->control); 322 /* Wait for controller to receive byte, and check ACK */ 323 return twsi_wait(twsi, expected_status, tick); 324 } 325 326 /* 327 * twsi_recv() - Receive a byte on the I2C bus. 328 * 329 * The static variable mvtwsi_control_flags controls whether we ack or nak. 330 * 331 * @twsi: The MVTWSI register structure to use. 332 * @byte: The byte to send. 333 * @ack_flag: Flag that determines whether the received byte should 334 * be acknowledged by the controller or not (sent ACK/NAK). 335 * @tick: The duration of a clock cycle at the current I2C speed. 336 * @return Zero if status is as expected, or a non-zero code if either a time 337 * out occurred or the status was not the expected one. 338 */ 339 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag, 340 uint tick) 341 { 342 int expected_status, status, control; 343 344 /* Compute expected status based on passed ACK flag */ 345 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK : 346 MVTWSI_STATUS_DATA_R_NAK; 347 /* Acknowledge *previous state*, and launch receive */ 348 control = MVTWSI_CONTROL_TWSIEN; 349 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0; 350 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 351 /* Wait for controller to receive byte, and assert ACK or NAK */ 352 status = twsi_wait(twsi, expected_status, tick); 353 /* If we did receive the expected byte, store it */ 354 if (status == 0) 355 *byte = readl(&twsi->data); 356 return status; 357 } 358 359 /* 360 * twsi_stop() - Assert a STOP condition on the bus. 361 * 362 * This function is also used to force the bus back to idle state (SDA = 363 * SCL = 1). 364 * 365 * @twsi: The MVTWSI register structure to use. 366 * @tick: The duration of a clock cycle at the current I2C speed. 367 * @return Zero if the operation succeeded, or a non-zero code if a time out 368 * occurred. 369 */ 370 static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) 371 { 372 int control, stop_status; 373 int status = 0; 374 int timeout = 1000; 375 376 /* Assert STOP */ 377 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; 378 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 379 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */ 380 do { 381 stop_status = readl(&twsi->status); 382 if (stop_status == MVTWSI_STATUS_IDLE) 383 break; 384 ndelay(tick); /* One clock cycle */ 385 } while (timeout--); 386 control = readl(&twsi->control); 387 if (stop_status != MVTWSI_STATUS_IDLE) 388 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT, 389 control, status, MVTWSI_STATUS_IDLE); 390 return status; 391 } 392 393 /* 394 * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters. 395 * 396 * @n: Parameter 'n' for the frequency calculation algorithm. 397 * @m: Parameter 'm' for the frequency calculation algorithm. 398 * @return The I2C frequency corresponding to the passed m and n parameters. 399 */ 400 static uint twsi_calc_freq(const int n, const int m) 401 { 402 #ifdef CONFIG_ARCH_SUNXI 403 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); 404 #else 405 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); 406 #endif 407 } 408 409 /* 410 * twsi_reset() - Reset the I2C controller. 411 * 412 * Resetting the controller also resets the baud rate and slave address, hence 413 * they must be re-established after the reset. 414 * 415 * @twsi: The MVTWSI register structure to use. 416 */ 417 static void twsi_reset(struct mvtwsi_registers *twsi) 418 { 419 /* Reset controller */ 420 writel(0, &twsi->soft_reset); 421 /* Wait 2 ms -- this is what the Marvell LSP does */ 422 udelay(20000); 423 } 424 425 /* 426 * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller. 427 * 428 * This function sets baud rate to the highest possible value that does not 429 * exceed the requested rate. 430 * 431 * @twsi: The MVTWSI register structure to use. 432 * @requested_speed: The desired frequency the controller should run at 433 * in Hz. 434 * @return The actual frequency the controller was configured to. 435 */ 436 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi, 437 uint requested_speed) 438 { 439 uint tmp_speed, highest_speed, n, m; 440 uint baud = 0x44; /* Baud rate after controller reset */ 441 442 highest_speed = 0; 443 /* Successively try m, n combinations, and use the combination 444 * resulting in the largest speed that's not above the requested 445 * speed */ 446 for (n = 0; n < 8; n++) { 447 for (m = 0; m < 16; m++) { 448 tmp_speed = twsi_calc_freq(n, m); 449 if ((tmp_speed <= requested_speed) && 450 (tmp_speed > highest_speed)) { 451 highest_speed = tmp_speed; 452 baud = (m << 3) | n; 453 } 454 } 455 } 456 writel(baud, &twsi->baudrate); 457 458 /* Wait for controller for one tick */ 459 #ifdef CONFIG_DM_I2C 460 ndelay(calc_tick(highest_speed)); 461 #else 462 ndelay(10000); 463 #endif 464 return highest_speed; 465 } 466 467 /* 468 * __twsi_i2c_init() - Initialize the I2C controller. 469 * 470 * @twsi: The MVTWSI register structure to use. 471 * @speed: The initial frequency the controller should run at 472 * in Hz. 473 * @slaveadd: The I2C address to be set for the I2C master. 474 * @actual_speed: A output parameter that receives the actual frequency 475 * in Hz the controller was set to by the function. 476 * @return Zero if the operation succeeded, or a non-zero code if a time out 477 * occurred. 478 */ 479 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, 480 int slaveadd, uint *actual_speed) 481 { 482 /* Reset controller */ 483 twsi_reset(twsi); 484 /* Set speed */ 485 *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed); 486 /* Set slave address; even though we don't use it */ 487 writel(slaveadd, &twsi->slave_address); 488 writel(0, &twsi->xtnd_slave_addr); 489 /* Assert STOP, but don't care for the result */ 490 #ifdef CONFIG_DM_I2C 491 (void) twsi_stop(twsi, calc_tick(*actual_speed)); 492 #else 493 (void) twsi_stop(twsi, 10000); 494 #endif 495 } 496 497 /* 498 * i2c_begin() - Start a I2C transaction. 499 * 500 * Begin a I2C transaction with a given expected start status and chip address. 501 * A START is asserted, and the address byte is sent to the I2C controller. The 502 * expected address status will be derived from the direction bit (bit 0) of 503 * the address byte. 504 * 505 * @twsi: The MVTWSI register structure to use. 506 * @expected_start_status: The I2C status the controller is expected to 507 * assert after the address byte was sent. 508 * @addr: The address byte to be sent. 509 * @tick: The duration of a clock cycle at the current 510 * I2C speed. 511 * @return Zero if the operation succeeded, or a non-zero code if a time out or 512 * unexpected I2C status occurred. 513 */ 514 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status, 515 u8 addr, uint tick) 516 { 517 int status, expected_addr_status; 518 519 /* Compute the expected address status from the direction bit in 520 * the address byte */ 521 if (addr & 1) /* Reading */ 522 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; 523 else /* Writing */ 524 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; 525 /* Assert START */ 526 status = twsi_start(twsi, expected_start_status, tick); 527 /* Send out the address if the start went well */ 528 if (status == 0) 529 status = twsi_send(twsi, addr, expected_addr_status, tick); 530 /* Return 0, or the status of the first failure */ 531 return status; 532 } 533 534 /* 535 * __twsi_i2c_probe_chip() - Probe the given I2C chip address. 536 * 537 * This function begins a I2C read transaction, does a dummy read and NAKs; if 538 * the procedure succeeds, the chip is considered to be present. 539 * 540 * @twsi: The MVTWSI register structure to use. 541 * @chip: The chip address to probe. 542 * @tick: The duration of a clock cycle at the current I2C speed. 543 * @return Zero if the operation succeeded, or a non-zero code if a time out or 544 * unexpected I2C status occurred. 545 */ 546 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip, 547 uint tick) 548 { 549 u8 dummy_byte; 550 int status; 551 552 /* Begin i2c read */ 553 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick); 554 /* Dummy read was accepted: receive byte, but NAK it. */ 555 if (status == 0) 556 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick); 557 /* Stop transaction */ 558 twsi_stop(twsi, tick); 559 /* Return 0, or the status of the first failure */ 560 return status; 561 } 562 563 /* 564 * __twsi_i2c_read() - Read data from a I2C chip. 565 * 566 * This function begins a I2C write transaction, and transmits the address 567 * bytes; then begins a I2C read transaction, and receives the data bytes. 568 * 569 * NOTE: Some devices want a stop right before the second start, while some 570 * will choke if it is there. Since deciding this is not yet supported in 571 * higher level APIs, we need to make a decision here, and for the moment that 572 * will be a repeated start without a preceding stop. 573 * 574 * @twsi: The MVTWSI register structure to use. 575 * @chip: The chip address to read from. 576 * @addr: The address bytes to send. 577 * @alen: The length of the address bytes in bytes. 578 * @data: The buffer to receive the data read from the chip (has to have 579 * a size of at least 'length' bytes). 580 * @length: The amount of data to be read from the chip in bytes. 581 * @tick: The duration of a clock cycle at the current I2C speed. 582 * @return Zero if the operation succeeded, or a non-zero code if a time out or 583 * unexpected I2C status occurred. 584 */ 585 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, 586 u8 *addr, int alen, uchar *data, int length, 587 uint tick) 588 { 589 int status = 0; 590 int stop_status; 591 int expected_start = MVTWSI_STATUS_START; 592 593 if (alen > 0) { 594 /* Begin i2c write to send the address bytes */ 595 status = i2c_begin(twsi, expected_start, (chip << 1), tick); 596 /* Send address bytes */ 597 while ((status == 0) && alen--) 598 status = twsi_send(twsi, addr[alen], 599 MVTWSI_STATUS_DATA_W_ACK, tick); 600 /* Send repeated STARTs after the initial START */ 601 expected_start = MVTWSI_STATUS_REPEATED_START; 602 } 603 /* Begin i2c read to receive data bytes */ 604 if (status == 0) 605 status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick); 606 /* Receive actual data bytes; set NAK if we if we have nothing more to 607 * read */ 608 while ((status == 0) && length--) 609 status = twsi_recv(twsi, data++, 610 length > 0 ? 611 MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick); 612 /* Stop transaction */ 613 stop_status = twsi_stop(twsi, tick); 614 /* Return 0, or the status of the first failure */ 615 return status != 0 ? status : stop_status; 616 } 617 618 /* 619 * __twsi_i2c_write() - Send data to a I2C chip. 620 * 621 * This function begins a I2C write transaction, and transmits the address 622 * bytes; then begins a new I2C write transaction, and sends the data bytes. 623 * 624 * @twsi: The MVTWSI register structure to use. 625 * @chip: The chip address to read from. 626 * @addr: The address bytes to send. 627 * @alen: The length of the address bytes in bytes. 628 * @data: The buffer containing the data to be sent to the chip. 629 * @length: The length of data to be sent to the chip in bytes. 630 * @tick: The duration of a clock cycle at the current I2C speed. 631 * @return Zero if the operation succeeded, or a non-zero code if a time out or 632 * unexpected I2C status occurred. 633 */ 634 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, 635 u8 *addr, int alen, uchar *data, int length, 636 uint tick) 637 { 638 int status, stop_status; 639 640 /* Begin i2c write to send first the address bytes, then the 641 * data bytes */ 642 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick); 643 /* Send address bytes */ 644 while ((status == 0) && (alen-- > 0)) 645 status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK, 646 tick); 647 /* Send data bytes */ 648 while ((status == 0) && (length-- > 0)) 649 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK, 650 tick); 651 /* Stop transaction */ 652 stop_status = twsi_stop(twsi, tick); 653 /* Return 0, or the status of the first failure */ 654 return status != 0 ? status : stop_status; 655 } 656 657 #ifndef CONFIG_DM_I2C 658 static void twsi_i2c_init(struct i2c_adapter *adap, int speed, 659 int slaveadd) 660 { 661 struct mvtwsi_registers *twsi = twsi_get_base(adap); 662 __twsi_i2c_init(twsi, speed, slaveadd, NULL); 663 } 664 665 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap, 666 uint requested_speed) 667 { 668 struct mvtwsi_registers *twsi = twsi_get_base(adap); 669 __twsi_i2c_set_bus_speed(twsi, requested_speed); 670 return 0; 671 } 672 673 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) 674 { 675 struct mvtwsi_registers *twsi = twsi_get_base(adap); 676 return __twsi_i2c_probe_chip(twsi, chip, 10000); 677 } 678 679 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 680 int alen, uchar *data, int length) 681 { 682 struct mvtwsi_registers *twsi = twsi_get_base(adap); 683 u8 addr_bytes[4]; 684 685 addr_bytes[0] = (addr >> 0) & 0xFF; 686 addr_bytes[1] = (addr >> 8) & 0xFF; 687 addr_bytes[2] = (addr >> 16) & 0xFF; 688 addr_bytes[3] = (addr >> 24) & 0xFF; 689 690 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length, 691 10000); 692 } 693 694 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 695 int alen, uchar *data, int length) 696 { 697 struct mvtwsi_registers *twsi = twsi_get_base(adap); 698 u8 addr_bytes[4]; 699 700 addr_bytes[0] = (addr >> 0) & 0xFF; 701 addr_bytes[1] = (addr >> 8) & 0xFF; 702 addr_bytes[2] = (addr >> 16) & 0xFF; 703 addr_bytes[3] = (addr >> 24) & 0xFF; 704 705 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length, 706 10000); 707 } 708 709 #ifdef CONFIG_I2C_MVTWSI_BASE0 710 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, 711 twsi_i2c_read, twsi_i2c_write, 712 twsi_i2c_set_bus_speed, 713 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 714 #endif 715 #ifdef CONFIG_I2C_MVTWSI_BASE1 716 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, 717 twsi_i2c_read, twsi_i2c_write, 718 twsi_i2c_set_bus_speed, 719 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) 720 721 #endif 722 #ifdef CONFIG_I2C_MVTWSI_BASE2 723 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe, 724 twsi_i2c_read, twsi_i2c_write, 725 twsi_i2c_set_bus_speed, 726 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) 727 728 #endif 729 #ifdef CONFIG_I2C_MVTWSI_BASE3 730 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe, 731 twsi_i2c_read, twsi_i2c_write, 732 twsi_i2c_set_bus_speed, 733 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) 734 735 #endif 736 #ifdef CONFIG_I2C_MVTWSI_BASE4 737 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, 738 twsi_i2c_read, twsi_i2c_write, 739 twsi_i2c_set_bus_speed, 740 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) 741 742 #endif 743 #ifdef CONFIG_I2C_MVTWSI_BASE5 744 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, 745 twsi_i2c_read, twsi_i2c_write, 746 twsi_i2c_set_bus_speed, 747 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) 748 749 #endif 750 #else /* CONFIG_DM_I2C */ 751 752 static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 753 u32 chip_flags) 754 { 755 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 756 return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick); 757 } 758 759 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed) 760 { 761 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 762 763 dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed); 764 dev->tick = calc_tick(dev->speed); 765 766 return 0; 767 } 768 769 static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus) 770 { 771 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 772 773 dev->base = dev_get_addr_ptr(bus); 774 775 if (!dev->base) 776 return -ENOMEM; 777 778 dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 779 "cell-index", -1); 780 dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 781 "u-boot,i2c-slave-addr", 0x0); 782 dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 783 "clock-frequency", 100000); 784 return 0; 785 } 786 787 static int mvtwsi_i2c_probe(struct udevice *bus) 788 { 789 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 790 uint actual_speed; 791 792 __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); 793 dev->speed = actual_speed; 794 dev->tick = calc_tick(dev->speed); 795 return 0; 796 } 797 798 static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 799 { 800 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 801 struct i2c_msg *dmsg, *omsg, dummy; 802 803 memset(&dummy, 0, sizeof(struct i2c_msg)); 804 805 /* We expect either two messages (one with an offset and one with the 806 * actual data) or one message (just data or offset/data combined) */ 807 if (nmsgs > 2 || nmsgs == 0) { 808 debug("%s: Only one or two messages are supported.", __func__); 809 return -1; 810 } 811 812 omsg = nmsgs == 1 ? &dummy : msg; 813 dmsg = nmsgs == 1 ? msg : msg + 1; 814 815 if (dmsg->flags & I2C_M_RD) 816 return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf, 817 omsg->len, dmsg->buf, dmsg->len, 818 dev->tick); 819 else 820 return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf, 821 omsg->len, dmsg->buf, dmsg->len, 822 dev->tick); 823 } 824 825 static const struct dm_i2c_ops mvtwsi_i2c_ops = { 826 .xfer = mvtwsi_i2c_xfer, 827 .probe_chip = mvtwsi_i2c_probe_chip, 828 .set_bus_speed = mvtwsi_i2c_set_bus_speed, 829 }; 830 831 static const struct udevice_id mvtwsi_i2c_ids[] = { 832 { .compatible = "marvell,mv64xxx-i2c", }, 833 { .compatible = "marvell,mv78230-i2c", }, 834 { /* sentinel */ } 835 }; 836 837 U_BOOT_DRIVER(i2c_mvtwsi) = { 838 .name = "i2c_mvtwsi", 839 .id = UCLASS_I2C, 840 .of_match = mvtwsi_i2c_ids, 841 .probe = mvtwsi_i2c_probe, 842 .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata, 843 .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev), 844 .ops = &mvtwsi_i2c_ops, 845 }; 846 #endif /* CONFIG_DM_I2C */ 847