1 /* 2 * Driver for the TWSI (i2c) controller found on the Marvell 3 * orion5x and kirkwood SoC families. 4 * 5 * Author: Albert Aribaud <albert.u.boot@aribaud.net> 6 * Copyright (c) 2010 Albert Aribaud. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <asm/io.h> 15 16 /* 17 * include a file that will provide CONFIG_I2C_MVTWSI_BASE* 18 * and possibly other settings 19 */ 20 21 #if defined(CONFIG_ORION5X) 22 #include <asm/arch/orion5x.h> 23 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) 24 #include <asm/arch/soc.h> 25 #elif defined(CONFIG_SUNXI) 26 #include <asm/arch/i2c.h> 27 #else 28 #error Driver mvtwsi not supported by SoC or board 29 #endif 30 31 /* 32 * TWSI register structure 33 */ 34 35 #ifdef CONFIG_SUNXI 36 37 struct mvtwsi_registers { 38 u32 slave_address; 39 u32 xtnd_slave_addr; 40 u32 data; 41 u32 control; 42 u32 status; 43 u32 baudrate; 44 u32 soft_reset; 45 }; 46 47 #else 48 49 struct mvtwsi_registers { 50 u32 slave_address; 51 u32 data; 52 u32 control; 53 union { 54 u32 status; /* when reading */ 55 u32 baudrate; /* when writing */ 56 }; 57 u32 xtnd_slave_addr; 58 u32 reserved[2]; 59 u32 soft_reset; 60 }; 61 62 #endif 63 64 /* 65 * Control register fields 66 */ 67 68 #define MVTWSI_CONTROL_ACK 0x00000004 69 #define MVTWSI_CONTROL_IFLG 0x00000008 70 #define MVTWSI_CONTROL_STOP 0x00000010 71 #define MVTWSI_CONTROL_START 0x00000020 72 #define MVTWSI_CONTROL_TWSIEN 0x00000040 73 #define MVTWSI_CONTROL_INTEN 0x00000080 74 75 /* 76 * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1, 77 * on other platforms it is a normal r/w bit which is cleared by writing 0. 78 */ 79 80 #ifdef CONFIG_SUNXI_GEN_SUN6I 81 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 82 #else 83 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 84 #endif 85 86 /* 87 * Status register values -- only those expected in normal master 88 * operation on non-10-bit-address devices; whatever status we don't 89 * expect in nominal conditions (bus errors, arbitration losses, 90 * missing ACKs...) we just pass back to the caller as an error 91 * code. 92 */ 93 94 #define MVTWSI_STATUS_START 0x08 95 #define MVTWSI_STATUS_REPEATED_START 0x10 96 #define MVTWSI_STATUS_ADDR_W_ACK 0x18 97 #define MVTWSI_STATUS_DATA_W_ACK 0x28 98 #define MVTWSI_STATUS_ADDR_R_ACK 0x40 99 #define MVTWSI_STATUS_ADDR_R_NAK 0x48 100 #define MVTWSI_STATUS_DATA_R_ACK 0x50 101 #define MVTWSI_STATUS_DATA_R_NAK 0x58 102 #define MVTWSI_STATUS_IDLE 0xF8 103 104 /* 105 * MVTWSI controller base 106 */ 107 108 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) 109 { 110 switch (adap->hwadapnr) { 111 #ifdef CONFIG_I2C_MVTWSI_BASE0 112 case 0: 113 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0; 114 #endif 115 #ifdef CONFIG_I2C_MVTWSI_BASE1 116 case 1: 117 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1; 118 #endif 119 #ifdef CONFIG_I2C_MVTWSI_BASE2 120 case 2: 121 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2; 122 #endif 123 #ifdef CONFIG_I2C_MVTWSI_BASE3 124 case 3: 125 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3; 126 #endif 127 #ifdef CONFIG_I2C_MVTWSI_BASE4 128 case 4: 129 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4; 130 #endif 131 #ifdef CONFIG_I2C_MVTWSI_BASE5 132 case 5: 133 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5; 134 #endif 135 default: 136 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); 137 break; 138 } 139 140 return NULL; 141 } 142 143 /* 144 * Returned statuses are 0 for success and nonzero otherwise. 145 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. 146 * Thus to ease debugging, the return status contains some debug info: 147 * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'. 148 * - bits 23..16 are the last value of the control register. 149 * - bits 15..8 are the last value of the status register. 150 * - bits 7..0 are the expected value of the status register. 151 */ 152 153 #define MVTWSI_ERROR_WRONG_STATUS 0x01 154 #define MVTWSI_ERROR_TIMEOUT 0x02 155 156 #define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \ 157 ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF)) 158 159 /* 160 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, 161 * return 0 (ok) or return 'wrong status'. 162 */ 163 static int twsi_wait(struct i2c_adapter *adap, int expected_status) 164 { 165 struct mvtwsi_registers *twsi = twsi_get_base(adap); 166 int control, status; 167 int timeout = 1000; 168 169 do { 170 control = readl(&twsi->control); 171 if (control & MVTWSI_CONTROL_IFLG) { 172 status = readl(&twsi->status); 173 if (status == expected_status) 174 return 0; 175 else 176 return MVTWSI_ERROR( 177 MVTWSI_ERROR_WRONG_STATUS, 178 control, status, expected_status); 179 } 180 udelay(10); /* one clock cycle at 100 kHz */ 181 } while (timeout--); 182 status = readl(&twsi->status); 183 return MVTWSI_ERROR( 184 MVTWSI_ERROR_TIMEOUT, control, status, expected_status); 185 } 186 187 /* 188 * These flags are ORed to any write to the control register 189 * They allow global setting of TWSIEN and ACK. 190 * By default none are set. 191 * twsi_start() sets TWSIEN (in case the controller was disabled) 192 * twsi_recv() sets ACK or resets it depending on expected status. 193 */ 194 static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; 195 196 /* 197 * Assert the START condition, either in a single I2C transaction 198 * or inside back-to-back ones (repeated starts). 199 */ 200 static int twsi_start(struct i2c_adapter *adap, int expected_status) 201 { 202 struct mvtwsi_registers *twsi = twsi_get_base(adap); 203 204 /* globally set TWSIEN in case it was not */ 205 twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; 206 /* assert START */ 207 writel(twsi_control_flags | MVTWSI_CONTROL_START | 208 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 209 /* wait for controller to process START */ 210 return twsi_wait(adap, expected_status); 211 } 212 213 /* 214 * Send a byte (i2c address or data). 215 */ 216 static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status) 217 { 218 struct mvtwsi_registers *twsi = twsi_get_base(adap); 219 220 /* put byte in data register for sending */ 221 writel(byte, &twsi->data); 222 /* clear any pending interrupt -- that'll cause sending */ 223 writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 224 /* wait for controller to receive byte and check ACK */ 225 return twsi_wait(adap, expected_status); 226 } 227 228 /* 229 * Receive a byte. 230 * Global mvtwsi_control_flags variable says if we should ack or nak. 231 */ 232 static int twsi_recv(struct i2c_adapter *adap, u8 *byte) 233 { 234 struct mvtwsi_registers *twsi = twsi_get_base(adap); 235 int expected_status, status; 236 237 /* compute expected status based on ACK bit in global control flags */ 238 if (twsi_control_flags & MVTWSI_CONTROL_ACK) 239 expected_status = MVTWSI_STATUS_DATA_R_ACK; 240 else 241 expected_status = MVTWSI_STATUS_DATA_R_NAK; 242 /* acknowledge *previous state* and launch receive */ 243 writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 244 /* wait for controller to receive byte and assert ACK or NAK */ 245 status = twsi_wait(adap, expected_status); 246 /* if we did receive expected byte then store it */ 247 if (status == 0) 248 *byte = readl(&twsi->data); 249 /* return status */ 250 return status; 251 } 252 253 /* 254 * Assert the STOP condition. 255 * This is also used to force the bus back in idle (SDA=SCL=1). 256 */ 257 static int twsi_stop(struct i2c_adapter *adap, int status) 258 { 259 struct mvtwsi_registers *twsi = twsi_get_base(adap); 260 int control, stop_status; 261 int timeout = 1000; 262 263 /* assert STOP */ 264 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; 265 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 266 /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ 267 do { 268 stop_status = readl(&twsi->status); 269 if (stop_status == MVTWSI_STATUS_IDLE) 270 break; 271 udelay(10); /* one clock cycle at 100 kHz */ 272 } while (timeout--); 273 control = readl(&twsi->control); 274 if (stop_status != MVTWSI_STATUS_IDLE) 275 if (status == 0) 276 status = MVTWSI_ERROR( 277 MVTWSI_ERROR_TIMEOUT, 278 control, status, MVTWSI_STATUS_IDLE); 279 return status; 280 } 281 282 static unsigned int twsi_calc_freq(const int n, const int m) 283 { 284 #ifdef CONFIG_SUNXI 285 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); 286 #else 287 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); 288 #endif 289 } 290 291 /* 292 * Reset controller. 293 * Controller reset also resets the baud rate and slave address, so 294 * they must be re-established afterwards. 295 */ 296 static void twsi_reset(struct i2c_adapter *adap) 297 { 298 struct mvtwsi_registers *twsi = twsi_get_base(adap); 299 /* ensure controller will be enabled by any twsi*() function */ 300 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; 301 /* reset controller */ 302 writel(0, &twsi->soft_reset); 303 /* wait 2 ms -- this is what the Marvell LSP does */ 304 udelay(20000); 305 } 306 307 /* 308 * I2C init called by cmd_i2c when doing 'i2c reset'. 309 * Sets baud to the highest possible value not exceeding requested one. 310 */ 311 static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap, 312 unsigned int requested_speed) 313 { 314 struct mvtwsi_registers *twsi = twsi_get_base(adap); 315 unsigned int tmp_speed, highest_speed, n, m; 316 unsigned int baud = 0x44; /* baudrate at controller reset */ 317 318 /* use actual speed to collect progressively higher values */ 319 highest_speed = 0; 320 /* compute m, n setting for highest speed not above requested speed */ 321 for (n = 0; n < 8; n++) { 322 for (m = 0; m < 16; m++) { 323 tmp_speed = twsi_calc_freq(n, m); 324 if ((tmp_speed <= requested_speed) 325 && (tmp_speed > highest_speed)) { 326 highest_speed = tmp_speed; 327 baud = (m << 3) | n; 328 } 329 } 330 } 331 writel(baud, &twsi->baudrate); 332 return 0; 333 } 334 335 static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 336 { 337 struct mvtwsi_registers *twsi = twsi_get_base(adap); 338 339 /* reset controller */ 340 twsi_reset(adap); 341 /* set speed */ 342 twsi_i2c_set_bus_speed(adap, speed); 343 /* set slave address even though we don't use it */ 344 writel(slaveadd, &twsi->slave_address); 345 writel(0, &twsi->xtnd_slave_addr); 346 /* assert STOP but don't care for the result */ 347 (void) twsi_stop(adap, 0); 348 } 349 350 /* 351 * Begin I2C transaction with expected start status, at given address. 352 * Common to i2c_probe, i2c_read and i2c_write. 353 * Expected address status will derive from direction bit (bit 0) in addr. 354 */ 355 static int i2c_begin(struct i2c_adapter *adap, int expected_start_status, 356 u8 addr) 357 { 358 int status, expected_addr_status; 359 360 /* compute expected address status from direction bit in addr */ 361 if (addr & 1) /* reading */ 362 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; 363 else /* writing */ 364 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; 365 /* assert START */ 366 status = twsi_start(adap, expected_start_status); 367 /* send out the address if the start went well */ 368 if (status == 0) 369 status = twsi_send(adap, addr, expected_addr_status); 370 /* return ok or status of first failure to caller */ 371 return status; 372 } 373 374 /* 375 * I2C probe called by cmd_i2c when doing 'i2c probe'. 376 * Begin read, nak data byte, end. 377 */ 378 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) 379 { 380 u8 dummy_byte; 381 int status; 382 383 /* begin i2c read */ 384 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1); 385 /* dummy read was accepted: receive byte but NAK it. */ 386 if (status == 0) 387 status = twsi_recv(adap, &dummy_byte); 388 /* Stop transaction */ 389 twsi_stop(adap, 0); 390 /* return 0 or status of first failure */ 391 return status; 392 } 393 394 /* 395 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c 396 * Begin write, send address byte(s), begin read, receive data bytes, end. 397 * 398 * NOTE: some EEPROMS want a stop right before the second start, while 399 * some will choke if it is there. Deciding which we should do is eeprom 400 * stuff, not i2c, but at the moment the APIs won't let us put it in 401 * cmd_eeprom, so we have to choose here, and for the moment that'll be 402 * a repeated start without a preceding stop. 403 */ 404 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 405 int alen, uchar *data, int length) 406 { 407 int status; 408 409 /* begin i2c write to send the address bytes */ 410 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1)); 411 /* send addr bytes */ 412 while ((status == 0) && alen--) 413 status = twsi_send(adap, addr >> (8*alen), 414 MVTWSI_STATUS_DATA_W_ACK); 415 /* begin i2c read to receive eeprom data bytes */ 416 if (status == 0) 417 status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START, 418 (chip << 1) | 1); 419 /* prepare ACK if at least one byte must be received */ 420 if (length > 0) 421 twsi_control_flags |= MVTWSI_CONTROL_ACK; 422 /* now receive actual bytes */ 423 while ((status == 0) && length--) { 424 /* reset NAK if we if no more to read now */ 425 if (length == 0) 426 twsi_control_flags &= ~MVTWSI_CONTROL_ACK; 427 /* read current byte */ 428 status = twsi_recv(adap, data++); 429 } 430 /* Stop transaction */ 431 status = twsi_stop(adap, status); 432 /* return 0 or status of first failure */ 433 return status; 434 } 435 436 /* 437 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c 438 * Begin write, send address byte(s), send data bytes, end. 439 */ 440 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 441 int alen, uchar *data, int length) 442 { 443 int status; 444 445 /* begin i2c write to send the eeprom adress bytes then data bytes */ 446 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1)); 447 /* send addr bytes */ 448 while ((status == 0) && alen--) 449 status = twsi_send(adap, addr >> (8*alen), 450 MVTWSI_STATUS_DATA_W_ACK); 451 /* send data bytes */ 452 while ((status == 0) && (length-- > 0)) 453 status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK); 454 /* Stop transaction */ 455 status = twsi_stop(adap, status); 456 /* return 0 or status of first failure */ 457 return status; 458 } 459 460 #ifdef CONFIG_I2C_MVTWSI_BASE0 461 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, 462 twsi_i2c_read, twsi_i2c_write, 463 twsi_i2c_set_bus_speed, 464 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 465 #endif 466 #ifdef CONFIG_I2C_MVTWSI_BASE1 467 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, 468 twsi_i2c_read, twsi_i2c_write, 469 twsi_i2c_set_bus_speed, 470 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) 471 472 #endif 473 #ifdef CONFIG_I2C_MVTWSI_BASE2 474 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe, 475 twsi_i2c_read, twsi_i2c_write, 476 twsi_i2c_set_bus_speed, 477 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) 478 479 #endif 480 #ifdef CONFIG_I2C_MVTWSI_BASE3 481 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe, 482 twsi_i2c_read, twsi_i2c_write, 483 twsi_i2c_set_bus_speed, 484 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) 485 486 #endif 487 #ifdef CONFIG_I2C_MVTWSI_BASE4 488 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, 489 twsi_i2c_read, twsi_i2c_write, 490 twsi_i2c_set_bus_speed, 491 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) 492 493 #endif 494 #ifdef CONFIG_I2C_MVTWSI_BASE5 495 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, 496 twsi_i2c_read, twsi_i2c_write, 497 twsi_i2c_set_bus_speed, 498 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) 499 500 #endif 501