1 /* 2 * (C) Copyright 2011 3 * Marvell Inc, <www.marvell.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _MV_I2C_H_ 25 #define _MV_I2C_H_ 26 extern void i2c_clk_enable(void); 27 28 /* Shall the current transfer have a start/stop condition? */ 29 #define I2C_COND_NORMAL 0 30 #define I2C_COND_START 1 31 #define I2C_COND_STOP 2 32 33 /* Shall the current transfer be ack/nacked or being waited for it? */ 34 #define I2C_ACKNAK_WAITACK 1 35 #define I2C_ACKNAK_SENDACK 2 36 #define I2C_ACKNAK_SENDNAK 4 37 38 /* Specify who shall transfer the data (master or slave) */ 39 #define I2C_READ 0 40 #define I2C_WRITE 1 41 42 #if (CONFIG_SYS_I2C_SPEED == 400000) 43 #define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \ 44 | ICR_SCLE) 45 #else 46 #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) 47 #endif 48 49 #define I2C_ISR_INIT 0x7FF 50 /* ----- Control register bits ---------------------------------------- */ 51 52 #define ICR_START 0x1 /* start bit */ 53 #define ICR_STOP 0x2 /* stop bit */ 54 #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ 55 #define ICR_TB 0x8 /* transfer byte bit */ 56 #define ICR_MA 0x10 /* master abort */ 57 #define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ 58 #define ICR_IUE 0x40 /* unit enable */ 59 #define ICR_GCD 0x80 /* general call disable */ 60 #define ICR_ITEIE 0x100 /* enable tx interrupts */ 61 #define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ 62 #define ICR_BEIE 0x400 /* enable bus error ints */ 63 #define ICR_SSDIE 0x800 /* slave STOP detected int enable */ 64 #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ 65 #define ICR_SADIE 0x2000 /* slave address detected int enable */ 66 #define ICR_UR 0x4000 /* unit reset */ 67 #define ICR_FM 0x8000 /* Fast Mode */ 68 69 /* ----- Status register bits ----------------------------------------- */ 70 71 #define ISR_RWM 0x1 /* read/write mode */ 72 #define ISR_ACKNAK 0x2 /* ack/nak status */ 73 #define ISR_UB 0x4 /* unit busy */ 74 #define ISR_IBB 0x8 /* bus busy */ 75 #define ISR_SSD 0x10 /* slave stop detected */ 76 #define ISR_ALD 0x20 /* arbitration loss detected */ 77 #define ISR_ITE 0x40 /* tx buffer empty */ 78 #define ISR_IRF 0x80 /* rx buffer full */ 79 #define ISR_GCAD 0x100 /* general call address detected */ 80 #define ISR_SAD 0x200 /* slave address detected */ 81 #define ISR_BED 0x400 /* bus error no ACK/NAK */ 82 83 #endif 84