13df619ecSLei Wen /* 23df619ecSLei Wen * (C) Copyright 2011 33df619ecSLei Wen * Marvell Inc, <www.marvell.com> 43df619ecSLei Wen * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 63df619ecSLei Wen */ 73df619ecSLei Wen 83df619ecSLei Wen #ifndef _MV_I2C_H_ 93df619ecSLei Wen #define _MV_I2C_H_ 103df619ecSLei Wen extern void i2c_clk_enable(void); 113df619ecSLei Wen 123df619ecSLei Wen /* Shall the current transfer have a start/stop condition? */ 133df619ecSLei Wen #define I2C_COND_NORMAL 0 143df619ecSLei Wen #define I2C_COND_START 1 153df619ecSLei Wen #define I2C_COND_STOP 2 163df619ecSLei Wen 173df619ecSLei Wen /* Shall the current transfer be ack/nacked or being waited for it? */ 183df619ecSLei Wen #define I2C_ACKNAK_WAITACK 1 193df619ecSLei Wen #define I2C_ACKNAK_SENDACK 2 203df619ecSLei Wen #define I2C_ACKNAK_SENDNAK 4 213df619ecSLei Wen 223df619ecSLei Wen /* Specify who shall transfer the data (master or slave) */ 233df619ecSLei Wen #define I2C_READ 0 243df619ecSLei Wen #define I2C_WRITE 1 253df619ecSLei Wen 263df619ecSLei Wen #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) 273df619ecSLei Wen 283df619ecSLei Wen #define I2C_ISR_INIT 0x7FF 293df619ecSLei Wen /* ----- Control register bits ---------------------------------------- */ 303df619ecSLei Wen 313df619ecSLei Wen #define ICR_START 0x1 /* start bit */ 323df619ecSLei Wen #define ICR_STOP 0x2 /* stop bit */ 333df619ecSLei Wen #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ 343df619ecSLei Wen #define ICR_TB 0x8 /* transfer byte bit */ 353df619ecSLei Wen #define ICR_MA 0x10 /* master abort */ 363df619ecSLei Wen #define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ 373df619ecSLei Wen #define ICR_IUE 0x40 /* unit enable */ 383df619ecSLei Wen #define ICR_GCD 0x80 /* general call disable */ 393df619ecSLei Wen #define ICR_ITEIE 0x100 /* enable tx interrupts */ 403df619ecSLei Wen #define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ 413df619ecSLei Wen #define ICR_BEIE 0x400 /* enable bus error ints */ 423df619ecSLei Wen #define ICR_SSDIE 0x800 /* slave STOP detected int enable */ 433df619ecSLei Wen #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ 443df619ecSLei Wen #define ICR_SADIE 0x2000 /* slave address detected int enable */ 453df619ecSLei Wen #define ICR_UR 0x4000 /* unit reset */ 46*9ad5a007SStefan Roese #ifdef CONFIG_ARMADA_3700 47*9ad5a007SStefan Roese #define ICR_SM 0x00000 /* Standard Mode */ 48*9ad5a007SStefan Roese #define ICR_FM 0x10000 /* Fast Mode */ 49*9ad5a007SStefan Roese #define ICR_MODE_MASK 0x30000 /* Mode mask */ 50*9ad5a007SStefan Roese #else 51*9ad5a007SStefan Roese #define ICR_SM 0x00000 /* Standard Mode */ 52*9ad5a007SStefan Roese #define ICR_FM 0x08000 /* Fast Mode */ 53*9ad5a007SStefan Roese #define ICR_MODE_MASK 0x18000 /* Mode mask */ 54*9ad5a007SStefan Roese #endif 553df619ecSLei Wen 563df619ecSLei Wen /* ----- Status register bits ----------------------------------------- */ 573df619ecSLei Wen 583df619ecSLei Wen #define ISR_RWM 0x1 /* read/write mode */ 593df619ecSLei Wen #define ISR_ACKNAK 0x2 /* ack/nak status */ 603df619ecSLei Wen #define ISR_UB 0x4 /* unit busy */ 613df619ecSLei Wen #define ISR_IBB 0x8 /* bus busy */ 623df619ecSLei Wen #define ISR_SSD 0x10 /* slave stop detected */ 633df619ecSLei Wen #define ISR_ALD 0x20 /* arbitration loss detected */ 643df619ecSLei Wen #define ISR_ITE 0x40 /* tx buffer empty */ 653df619ecSLei Wen #define ISR_IRF 0x80 /* rx buffer full */ 663df619ecSLei Wen #define ISR_GCAD 0x100 /* general call address detected */ 673df619ecSLei Wen #define ISR_SAD 0x200 /* slave address detected */ 683df619ecSLei Wen #define ISR_BED 0x400 /* bus error no ACK/NAK */ 693df619ecSLei Wen 703df619ecSLei Wen #endif 71