1*3df619ecSLei Wen /* 2*3df619ecSLei Wen * (C) Copyright 2011 3*3df619ecSLei Wen * Marvell Inc, <www.marvell.com> 4*3df619ecSLei Wen * 5*3df619ecSLei Wen * See file CREDITS for list of people who contributed to this 6*3df619ecSLei Wen * project. 7*3df619ecSLei Wen * 8*3df619ecSLei Wen * This program is free software; you can redistribute it and/or 9*3df619ecSLei Wen * modify it under the terms of the GNU General Public License as 10*3df619ecSLei Wen * published by the Free Software Foundation; either version 2 of 11*3df619ecSLei Wen * the License, or (at your option) any later version. 12*3df619ecSLei Wen * 13*3df619ecSLei Wen * This program is distributed in the hope that it will be useful, 14*3df619ecSLei Wen * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*3df619ecSLei Wen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*3df619ecSLei Wen * GNU General Public License for more details. 17*3df619ecSLei Wen * 18*3df619ecSLei Wen * You should have received a copy of the GNU General Public License 19*3df619ecSLei Wen * along with this program; if not, write to the Free Software 20*3df619ecSLei Wen * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*3df619ecSLei Wen * MA 02111-1307 USA 22*3df619ecSLei Wen */ 23*3df619ecSLei Wen 24*3df619ecSLei Wen #ifndef _MV_I2C_H_ 25*3df619ecSLei Wen #define _MV_I2C_H_ 26*3df619ecSLei Wen extern void i2c_clk_enable(void); 27*3df619ecSLei Wen 28*3df619ecSLei Wen /* Shall the current transfer have a start/stop condition? */ 29*3df619ecSLei Wen #define I2C_COND_NORMAL 0 30*3df619ecSLei Wen #define I2C_COND_START 1 31*3df619ecSLei Wen #define I2C_COND_STOP 2 32*3df619ecSLei Wen 33*3df619ecSLei Wen /* Shall the current transfer be ack/nacked or being waited for it? */ 34*3df619ecSLei Wen #define I2C_ACKNAK_WAITACK 1 35*3df619ecSLei Wen #define I2C_ACKNAK_SENDACK 2 36*3df619ecSLei Wen #define I2C_ACKNAK_SENDNAK 4 37*3df619ecSLei Wen 38*3df619ecSLei Wen /* Specify who shall transfer the data (master or slave) */ 39*3df619ecSLei Wen #define I2C_READ 0 40*3df619ecSLei Wen #define I2C_WRITE 1 41*3df619ecSLei Wen 42*3df619ecSLei Wen #if (CONFIG_SYS_I2C_SPEED == 400000) 43*3df619ecSLei Wen #define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \ 44*3df619ecSLei Wen | ICR_SCLE) 45*3df619ecSLei Wen #else 46*3df619ecSLei Wen #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) 47*3df619ecSLei Wen #endif 48*3df619ecSLei Wen 49*3df619ecSLei Wen #define I2C_ISR_INIT 0x7FF 50*3df619ecSLei Wen /* ----- Control register bits ---------------------------------------- */ 51*3df619ecSLei Wen 52*3df619ecSLei Wen #define ICR_START 0x1 /* start bit */ 53*3df619ecSLei Wen #define ICR_STOP 0x2 /* stop bit */ 54*3df619ecSLei Wen #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ 55*3df619ecSLei Wen #define ICR_TB 0x8 /* transfer byte bit */ 56*3df619ecSLei Wen #define ICR_MA 0x10 /* master abort */ 57*3df619ecSLei Wen #define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ 58*3df619ecSLei Wen #define ICR_IUE 0x40 /* unit enable */ 59*3df619ecSLei Wen #define ICR_GCD 0x80 /* general call disable */ 60*3df619ecSLei Wen #define ICR_ITEIE 0x100 /* enable tx interrupts */ 61*3df619ecSLei Wen #define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ 62*3df619ecSLei Wen #define ICR_BEIE 0x400 /* enable bus error ints */ 63*3df619ecSLei Wen #define ICR_SSDIE 0x800 /* slave STOP detected int enable */ 64*3df619ecSLei Wen #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ 65*3df619ecSLei Wen #define ICR_SADIE 0x2000 /* slave address detected int enable */ 66*3df619ecSLei Wen #define ICR_UR 0x4000 /* unit reset */ 67*3df619ecSLei Wen #define ICR_FM 0x8000 /* Fast Mode */ 68*3df619ecSLei Wen 69*3df619ecSLei Wen /* ----- Status register bits ----------------------------------------- */ 70*3df619ecSLei Wen 71*3df619ecSLei Wen #define ISR_RWM 0x1 /* read/write mode */ 72*3df619ecSLei Wen #define ISR_ACKNAK 0x2 /* ack/nak status */ 73*3df619ecSLei Wen #define ISR_UB 0x4 /* unit busy */ 74*3df619ecSLei Wen #define ISR_IBB 0x8 /* bus busy */ 75*3df619ecSLei Wen #define ISR_SSD 0x10 /* slave stop detected */ 76*3df619ecSLei Wen #define ISR_ALD 0x20 /* arbitration loss detected */ 77*3df619ecSLei Wen #define ISR_ITE 0x40 /* tx buffer empty */ 78*3df619ecSLei Wen #define ISR_IRF 0x80 /* rx buffer full */ 79*3df619ecSLei Wen #define ISR_GCAD 0x100 /* general call address detected */ 80*3df619ecSLei Wen #define ISR_SAD 0x200 /* slave address detected */ 81*3df619ecSLei Wen #define ISR_BED 0x400 /* bus error no ACK/NAK */ 82*3df619ecSLei Wen 83*3df619ecSLei Wen #endif 84