xref: /openbmc/u-boot/drivers/i2c/imx_lpi2c.c (revision 78a88f79)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2016 Freescale Semiconductors, Inc.
4  */
5 
6 #include <common.h>
7 #include <errno.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <imx_lpi2c.h>
12 #include <asm/arch/sys_proto.h>
13 #include <dm.h>
14 #include <fdtdec.h>
15 #include <i2c.h>
16 
17 #define LPI2C_FIFO_SIZE 4
18 #define LPI2C_NACK_TOUT_MS 1
19 #define LPI2C_TIMEOUT_MS 100
20 
21 static int bus_i2c_init(struct udevice *bus, int speed);
22 
23 /* Weak linked function for overridden by some SoC power function */
24 int __weak init_i2c_power(unsigned i2c_num)
25 {
26 	return 0;
27 }
28 
29 static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
30 {
31 	lpi2c_status_t result = LPI2C_SUCESS;
32 	u32 status;
33 
34 	status = readl(&regs->msr);
35 
36 	if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
37 		result = LPI2C_BUSY;
38 
39 	return result;
40 }
41 
42 static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
43 {
44 	lpi2c_status_t result = LPI2C_SUCESS;
45 	u32 val, status;
46 
47 	status = readl(&regs->msr);
48 	/* errors to check for */
49 	status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
50 		LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
51 
52 	if (status) {
53 		if (status & LPI2C_MSR_PLTF_MASK)
54 			result = LPI2C_PIN_LOW_TIMEOUT_ERR;
55 		else if (status & LPI2C_MSR_ALF_MASK)
56 			result = LPI2C_ARB_LOST_ERR;
57 		else if (status & LPI2C_MSR_NDF_MASK)
58 			result = LPI2C_NAK_ERR;
59 		else if (status & LPI2C_MSR_FEF_MASK)
60 			result = LPI2C_FIFO_ERR;
61 
62 		/* clear status flags */
63 		writel(0x7f00, &regs->msr);
64 		/* reset fifos */
65 		val = readl(&regs->mcr);
66 		val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
67 		writel(val, &regs->mcr);
68 	}
69 
70 	return result;
71 }
72 
73 static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
74 {
75 	lpi2c_status_t result = LPI2C_SUCESS;
76 	u32 txcount = 0;
77 	ulong start_time = get_timer(0);
78 
79 	do {
80 		txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
81 		txcount = LPI2C_FIFO_SIZE - txcount;
82 		result = imx_lpci2c_check_clear_error(regs);
83 		if (result) {
84 			debug("i2c: wait for tx ready: result 0x%x\n", result);
85 			return result;
86 		}
87 		if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
88 			debug("i2c: wait for tx ready: timeout\n");
89 			return -1;
90 		}
91 	} while (!txcount);
92 
93 	return result;
94 }
95 
96 static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
97 {
98 	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
99 	lpi2c_status_t result = LPI2C_SUCESS;
100 
101 	/* empty tx */
102 	if (!len)
103 		return result;
104 
105 	while (len--) {
106 		result = bus_i2c_wait_for_tx_ready(regs);
107 		if (result) {
108 			debug("i2c: send wait fot tx ready: %d\n", result);
109 			return result;
110 		}
111 		writel(*txbuf++, &regs->mtdr);
112 	}
113 
114 	return result;
115 }
116 
117 static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
118 {
119 	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
120 	lpi2c_status_t result = LPI2C_SUCESS;
121 	u32 val;
122 	ulong start_time = get_timer(0);
123 
124 	/* empty read */
125 	if (!len)
126 		return result;
127 
128 	result = bus_i2c_wait_for_tx_ready(regs);
129 	if (result) {
130 		debug("i2c: receive wait fot tx ready: %d\n", result);
131 		return result;
132 	}
133 
134 	/* clear all status flags */
135 	writel(0x7f00, &regs->msr);
136 	/* send receive command */
137 	val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
138 	writel(val, &regs->mtdr);
139 
140 	while (len--) {
141 		do {
142 			result = imx_lpci2c_check_clear_error(regs);
143 			if (result) {
144 				debug("i2c: receive check clear error: %d\n",
145 				      result);
146 				return result;
147 			}
148 			if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
149 				debug("i2c: receive mrdr: timeout\n");
150 				return -1;
151 			}
152 			val = readl(&regs->mrdr);
153 		} while (val & LPI2C_MRDR_RXEMPTY_MASK);
154 		*rxbuf++ = LPI2C_MRDR_DATA(val);
155 	}
156 
157 	return result;
158 }
159 
160 static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
161 {
162 	lpi2c_status_t result;
163 	struct imx_lpi2c_reg *regs =
164 		(struct imx_lpi2c_reg *)devfdt_get_addr(bus);
165 	u32 val;
166 
167 	result = imx_lpci2c_check_busy_bus(regs);
168 	if (result) {
169 		debug("i2c: start check busy bus: 0x%x\n", result);
170 
171 		/* Try to init the lpi2c then check the bus busy again */
172 		bus_i2c_init(bus, 100000);
173 		result = imx_lpci2c_check_busy_bus(regs);
174 		if (result) {
175 			printf("i2c: Error check busy bus: 0x%x\n", result);
176 			return result;
177 		}
178 	}
179 	/* clear all status flags */
180 	writel(0x7f00, &regs->msr);
181 	/* turn off auto-stop condition */
182 	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
183 	writel(val, &regs->mcfgr1);
184 	/* wait tx fifo ready */
185 	result = bus_i2c_wait_for_tx_ready(regs);
186 	if (result) {
187 		debug("i2c: start wait for tx ready: 0x%x\n", result);
188 		return result;
189 	}
190 	/* issue start command */
191 	val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
192 	writel(val, &regs->mtdr);
193 
194 	return result;
195 }
196 
197 static int bus_i2c_stop(struct udevice *bus)
198 {
199 	lpi2c_status_t result;
200 	struct imx_lpi2c_reg *regs =
201 		(struct imx_lpi2c_reg *)devfdt_get_addr(bus);
202 	u32 status;
203 	ulong start_time;
204 
205 	result = bus_i2c_wait_for_tx_ready(regs);
206 	if (result) {
207 		debug("i2c: stop wait for tx ready: 0x%x\n", result);
208 		return result;
209 	}
210 
211 	/* send stop command */
212 	writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
213 
214 	start_time = get_timer(0);
215 	while (1) {
216 		status = readl(&regs->msr);
217 		result = imx_lpci2c_check_clear_error(regs);
218 		/* stop detect flag */
219 		if (status & LPI2C_MSR_SDF_MASK) {
220 			/* clear stop flag */
221 			status &= LPI2C_MSR_SDF_MASK;
222 			writel(status, &regs->msr);
223 			break;
224 		}
225 
226 		if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
227 			debug("stop timeout\n");
228 			return -ETIMEDOUT;
229 		}
230 	}
231 
232 	return result;
233 }
234 
235 static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
236 {
237 	lpi2c_status_t result;
238 
239 	result = bus_i2c_start(bus, chip, 1);
240 	if (result)
241 		return result;
242 	result = bus_i2c_receive(bus, buf, len);
243 	if (result)
244 		return result;
245 
246 	return result;
247 }
248 
249 static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
250 {
251 	lpi2c_status_t result;
252 
253 	result = bus_i2c_start(bus, chip, 0);
254 	if (result)
255 		return result;
256 	result = bus_i2c_send(bus, buf, len);
257 	if (result)
258 		return result;
259 
260 	return result;
261 }
262 
263 
264 static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
265 {
266 	struct imx_lpi2c_reg *regs;
267 	u32 val;
268 	u32 preescale = 0, best_pre = 0, clkhi = 0;
269 	u32 best_clkhi = 0, abs_error = 0, rate;
270 	u32 error = 0xffffffff;
271 	u32 clock_rate;
272 	bool mode;
273 	int i;
274 
275 	regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
276 	clock_rate = imx_get_i2cclk(bus->seq);
277 	if (!clock_rate)
278 		return -EPERM;
279 
280 	mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
281 	/* disable master mode */
282 	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
283 	writel(val | LPI2C_MCR_MEN(0), &regs->mcr);
284 
285 	for (preescale = 1; (preescale <= 128) &&
286 		(error != 0); preescale = 2 * preescale) {
287 		for (clkhi = 1; clkhi < 32; clkhi++) {
288 			if (clkhi == 1)
289 				rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
290 			else
291 				rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
292 
293 			abs_error = speed > rate ? speed - rate : rate - speed;
294 
295 			if (abs_error < error) {
296 				best_pre = preescale;
297 				best_clkhi = clkhi;
298 				error = abs_error;
299 				if (abs_error == 0)
300 					break;
301 			}
302 		}
303 	}
304 
305 	/* Standard, fast, fast mode plus and ultra-fast transfers. */
306 	val = LPI2C_MCCR0_CLKHI(best_clkhi);
307 	if (best_clkhi < 2)
308 		val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
309 	else
310 		val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
311 			LPI2C_MCCR0_DATAVD(best_clkhi / 2);
312 	writel(val, &regs->mccr0);
313 
314 	for (i = 0; i < 8; i++) {
315 		if (best_pre == (1 << i)) {
316 			best_pre = i;
317 			break;
318 		}
319 	}
320 
321 	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
322 	writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
323 
324 	if (mode) {
325 		val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
326 		writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
327 	}
328 
329 	return 0;
330 }
331 
332 static int bus_i2c_init(struct udevice *bus, int speed)
333 {
334 	struct imx_lpi2c_reg *regs;
335 	u32 val;
336 	int ret;
337 
338 	regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
339 	/* reset peripheral */
340 	writel(LPI2C_MCR_RST_MASK, &regs->mcr);
341 	writel(0x0, &regs->mcr);
342 	/* Disable Dozen mode */
343 	writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
344 	/* host request disable, active high, external pin */
345 	val = readl(&regs->mcfgr0);
346 	val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
347 				LPI2C_MCFGR0_HRSEL_MASK));
348 	val |= LPI2C_MCFGR0_HRPOL(0x1);
349 	writel(val, &regs->mcfgr0);
350 	/* pincfg and ignore ack */
351 	val = readl(&regs->mcfgr1);
352 	val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
353 	val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
354 	val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
355 	writel(val, &regs->mcfgr1);
356 
357 	ret = bus_i2c_set_bus_speed(bus, speed);
358 
359 	/* enable lpi2c in master mode */
360 	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
361 	writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
362 
363 	debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
364 
365 	return ret;
366 }
367 
368 static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
369 				u32 chip_flags)
370 {
371 	lpi2c_status_t result;
372 
373 	result = bus_i2c_start(bus, chip, 0);
374 	if (result) {
375 		bus_i2c_stop(bus);
376 		bus_i2c_init(bus, 100000);
377 		return result;
378 	}
379 
380 	result = bus_i2c_stop(bus);
381 	if (result)
382 		bus_i2c_init(bus, 100000);
383 
384 	return result;
385 }
386 
387 static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
388 {
389 	int ret = 0, ret_stop;
390 
391 	for (; nmsgs > 0; nmsgs--, msg++) {
392 		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
393 		if (msg->flags & I2C_M_RD)
394 			ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
395 		else {
396 			ret = bus_i2c_write(bus, msg->addr, msg->buf,
397 					    msg->len);
398 			if (ret)
399 				break;
400 		}
401 	}
402 
403 	if (ret)
404 		debug("i2c_write: error sending\n");
405 
406 	ret_stop = bus_i2c_stop(bus);
407 	if (ret_stop)
408 		debug("i2c_xfer: stop bus error\n");
409 
410 	ret |= ret_stop;
411 
412 	return ret;
413 }
414 
415 static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
416 {
417 	return bus_i2c_set_bus_speed(bus, speed);
418 }
419 
420 static int imx_lpi2c_probe(struct udevice *bus)
421 {
422 	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
423 	fdt_addr_t addr;
424 	int ret;
425 
426 	i2c_bus->driver_data = dev_get_driver_data(bus);
427 
428 	addr = devfdt_get_addr(bus);
429 	if (addr == FDT_ADDR_T_NONE)
430 		return -EINVAL;
431 
432 	i2c_bus->base = addr;
433 	i2c_bus->index = bus->seq;
434 	i2c_bus->bus = bus;
435 
436 	/* power up i2c resource */
437 	ret = init_i2c_power(bus->seq);
438 	if (ret) {
439 		debug("init_i2c_power err = %d\n", ret);
440 		return ret;
441 	}
442 
443 	/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
444 	ret = enable_i2c_clk(1, bus->seq);
445 	if (ret < 0)
446 		return ret;
447 
448 	ret = bus_i2c_init(bus, 100000);
449 	if (ret < 0)
450 		return ret;
451 
452 	debug("i2c : controller bus %d at %lu , speed %d: ",
453 	      bus->seq, i2c_bus->base,
454 	      i2c_bus->speed);
455 
456 	return 0;
457 }
458 
459 static const struct dm_i2c_ops imx_lpi2c_ops = {
460 	.xfer		= imx_lpi2c_xfer,
461 	.probe_chip	= imx_lpi2c_probe_chip,
462 	.set_bus_speed	= imx_lpi2c_set_bus_speed,
463 };
464 
465 static const struct udevice_id imx_lpi2c_ids[] = {
466 	{ .compatible = "fsl,imx7ulp-lpi2c", },
467 	{ .compatible = "fsl,imx8qm-lpi2c", },
468 	{}
469 };
470 
471 U_BOOT_DRIVER(imx_lpi2c) = {
472 	.name = "imx_lpi2c",
473 	.id = UCLASS_I2C,
474 	.of_match = imx_lpi2c_ids,
475 	.probe = imx_lpi2c_probe,
476 	.priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
477 	.ops = &imx_lpi2c_ops,
478 };
479