1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2013 4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #ifdef CONFIG_DM_I2C 10 #include <dm.h> 11 #include <fpgamap.h> 12 #include "../misc/gdsys_soc.h" 13 #else 14 #include <gdsys_fpga.h> 15 #endif 16 #include <asm/unaligned.h> 17 18 #ifdef CONFIG_DM_I2C 19 struct ihs_i2c_priv { 20 uint speed; 21 phys_addr_t addr; 22 }; 23 24 enum { 25 REG_INTERRUPT_STATUS = 0x00, 26 REG_INTERRUPT_ENABLE_CONTROL = 0x02, 27 REG_WRITE_MAILBOX_EXT = 0x04, 28 REG_WRITE_MAILBOX = 0x06, 29 REG_READ_MAILBOX_EXT = 0x08, 30 REG_READ_MAILBOX = 0x0A, 31 }; 32 33 #else /* !CONFIG_DM_I2C */ 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #ifdef CONFIG_SYS_I2C_IHS_DUAL 37 38 #define I2C_SET_REG(fld, val) \ 39 do { \ 40 if (I2C_ADAP_HWNR & 0x10) \ 41 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ 42 else \ 43 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ 44 } while (0) 45 #else 46 #define I2C_SET_REG(fld, val) \ 47 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val) 48 #endif 49 50 #ifdef CONFIG_SYS_I2C_IHS_DUAL 51 #define I2C_GET_REG(fld, val) \ 52 do { \ 53 if (I2C_ADAP_HWNR & 0x10) \ 54 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ 55 else \ 56 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ 57 } while (0) 58 #else 59 #define I2C_GET_REG(fld, val) \ 60 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val) 61 #endif 62 #endif /* CONFIG_DM_I2C */ 63 64 enum { 65 I2CINT_ERROR_EV = BIT(13), 66 I2CINT_TRANSMIT_EV = BIT(14), 67 I2CINT_RECEIVE_EV = BIT(15), 68 }; 69 70 enum { 71 I2CMB_READ = 0 << 10, 72 I2CMB_WRITE = 1 << 10, 73 I2CMB_1BYTE = 0 << 11, 74 I2CMB_2BYTE = 1 << 11, 75 I2CMB_DONT_HOLD_BUS = 0 << 13, 76 I2CMB_HOLD_BUS = 1 << 13, 77 I2CMB_NATIVE = 2 << 14, 78 }; 79 80 enum { 81 I2COP_WRITE = 0, 82 I2COP_READ = 1, 83 }; 84 85 #ifdef CONFIG_DM_I2C 86 static int wait_for_int(struct udevice *dev, int read) 87 #else 88 static int wait_for_int(bool read) 89 #endif 90 { 91 u16 val; 92 uint ctr = 0; 93 #ifdef CONFIG_DM_I2C 94 struct ihs_i2c_priv *priv = dev_get_priv(dev); 95 struct udevice *fpga; 96 97 gdsys_soc_get_fpga(dev, &fpga); 98 #endif 99 100 #ifdef CONFIG_DM_I2C 101 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, 102 FPGAMAP_SIZE_16); 103 #else 104 I2C_GET_REG(interrupt_status, &val); 105 #endif 106 /* Wait until error or receive/transmit interrupt was raised */ 107 while (!(val & (I2CINT_ERROR_EV 108 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { 109 udelay(10); 110 if (ctr++ > 5000) 111 return 1; 112 #ifdef CONFIG_DM_I2C 113 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, 114 FPGAMAP_SIZE_16); 115 #else 116 I2C_GET_REG(interrupt_status, &val); 117 #endif 118 } 119 120 return (val & I2CINT_ERROR_EV) ? 1 : 0; 121 } 122 123 #ifdef CONFIG_DM_I2C 124 static int ihs_i2c_transfer(struct udevice *dev, uchar chip, 125 uchar *buffer, int len, int read, bool is_last) 126 #else 127 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, 128 bool is_last) 129 #endif 130 { 131 u16 val; 132 u16 data; 133 #ifdef CONFIG_DM_I2C 134 struct ihs_i2c_priv *priv = dev_get_priv(dev); 135 struct udevice *fpga; 136 137 gdsys_soc_get_fpga(dev, &fpga); 138 #endif 139 140 /* Clear interrupt status */ 141 data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV; 142 #ifdef CONFIG_DM_I2C 143 fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data, 144 FPGAMAP_SIZE_16); 145 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, 146 FPGAMAP_SIZE_16); 147 #else 148 I2C_SET_REG(interrupt_status, data); 149 I2C_GET_REG(interrupt_status, &val); 150 #endif 151 152 /* If we want to write and have data, write the bytes to the mailbox */ 153 if (!read && len) { 154 val = buffer[0]; 155 156 if (len > 1) 157 val |= buffer[1] << 8; 158 #ifdef CONFIG_DM_I2C 159 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val, 160 FPGAMAP_SIZE_16); 161 #else 162 I2C_SET_REG(write_mailbox_ext, val); 163 #endif 164 } 165 166 data = I2CMB_NATIVE 167 | (read ? 0 : I2CMB_WRITE) 168 | (chip << 1) 169 | ((len > 1) ? I2CMB_2BYTE : 0) 170 | (is_last ? 0 : I2CMB_HOLD_BUS); 171 172 #ifdef CONFIG_DM_I2C 173 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data, 174 FPGAMAP_SIZE_16); 175 #else 176 I2C_SET_REG(write_mailbox, data); 177 #endif 178 179 #ifdef CONFIG_DM_I2C 180 if (wait_for_int(dev, read)) 181 #else 182 if (wait_for_int(read)) 183 #endif 184 return 1; 185 186 /* If we want to read, get the bytes from the mailbox */ 187 if (read) { 188 #ifdef CONFIG_DM_I2C 189 fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val, 190 FPGAMAP_SIZE_16); 191 #else 192 I2C_GET_REG(read_mailbox_ext, &val); 193 #endif 194 buffer[0] = val & 0xff; 195 if (len > 1) 196 buffer[1] = val >> 8; 197 } 198 199 return 0; 200 } 201 202 #ifdef CONFIG_DM_I2C 203 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read) 204 #else 205 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, 206 int read) 207 #endif 208 { 209 while (len) { 210 int transfer = min(len, 2); 211 bool is_last = len <= transfer; 212 213 #ifdef CONFIG_DM_I2C 214 if (ihs_i2c_transfer(dev, chip, data, transfer, read, 215 hold_bus ? false : is_last)) 216 return 1; 217 #else 218 if (ihs_i2c_transfer(chip, data, transfer, read, 219 hold_bus ? false : is_last)) 220 return 1; 221 #endif 222 223 data += transfer; 224 len -= transfer; 225 } 226 227 return 0; 228 } 229 230 #ifdef CONFIG_DM_I2C 231 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen, 232 bool hold_bus) 233 #else 234 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus) 235 #endif 236 { 237 #ifdef CONFIG_DM_I2C 238 return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE); 239 #else 240 return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE); 241 #endif 242 } 243 244 #ifdef CONFIG_DM_I2C 245 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr, 246 int alen, uchar *buffer, int len, int read) 247 #else 248 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, 249 int alen, uchar *buffer, int len, int read) 250 #endif 251 { 252 /* Don't hold the bus if length of data to send/receive is zero */ 253 #ifdef CONFIG_DM_I2C 254 if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len)) 255 return 1; 256 #else 257 if (len <= 0 || ihs_i2c_address(chip, addr, alen, len)) 258 return 1; 259 #endif 260 261 #ifdef CONFIG_DM_I2C 262 return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read); 263 #else 264 return ihs_i2c_send_buffer(chip, buffer, len, false, read); 265 #endif 266 } 267 268 #ifdef CONFIG_DM_I2C 269 270 int ihs_i2c_probe(struct udevice *bus) 271 { 272 struct ihs_i2c_priv *priv = dev_get_priv(bus); 273 int addr; 274 275 addr = dev_read_u32_default(bus, "reg", -1); 276 277 priv->addr = addr; 278 279 return 0; 280 } 281 282 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed) 283 { 284 struct ihs_i2c_priv *priv = dev_get_priv(bus); 285 286 if (speed != priv->speed && priv->speed != 0) 287 return 1; 288 289 priv->speed = speed; 290 291 return 0; 292 } 293 294 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 295 { 296 struct i2c_msg *dmsg, *omsg, dummy; 297 298 memset(&dummy, 0, sizeof(struct i2c_msg)); 299 300 /* We expect either two messages (one with an offset and one with the 301 * actucal data) or one message (just data) 302 */ 303 if (nmsgs > 2 || nmsgs == 0) { 304 debug("%s: Only one or two messages are supported.", __func__); 305 return -1; 306 } 307 308 omsg = nmsgs == 1 ? &dummy : msg; 309 dmsg = nmsgs == 1 ? msg : msg + 1; 310 311 if (dmsg->flags & I2C_M_RD) 312 return ihs_i2c_access(bus, dmsg->addr, omsg->buf, 313 omsg->len, dmsg->buf, dmsg->len, 314 I2COP_READ); 315 else 316 return ihs_i2c_access(bus, dmsg->addr, omsg->buf, 317 omsg->len, dmsg->buf, dmsg->len, 318 I2COP_WRITE); 319 } 320 321 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 322 u32 chip_flags) 323 { 324 uchar buffer[2]; 325 326 if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true)) 327 return 1; 328 329 return 0; 330 } 331 332 static const struct dm_i2c_ops ihs_i2c_ops = { 333 .xfer = ihs_i2c_xfer, 334 .probe_chip = ihs_i2c_probe_chip, 335 .set_bus_speed = ihs_i2c_set_bus_speed, 336 }; 337 338 static const struct udevice_id ihs_i2c_ids[] = { 339 { .compatible = "gdsys,ihs_i2cmaster", }, 340 { /* sentinel */ } 341 }; 342 343 U_BOOT_DRIVER(i2c_ihs) = { 344 .name = "i2c_ihs", 345 .id = UCLASS_I2C, 346 .of_match = ihs_i2c_ids, 347 .probe = ihs_i2c_probe, 348 .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv), 349 .ops = &ihs_i2c_ops, 350 }; 351 352 #else /* CONFIG_DM_I2C */ 353 354 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 355 { 356 #ifdef CONFIG_SYS_I2C_INIT_BOARD 357 /* 358 * Call board specific i2c bus reset routine before accessing the 359 * environment, which might be in a chip on that bus. For details 360 * about this problem see doc/I2C_Edge_Conditions. 361 */ 362 i2c_init_board(); 363 #endif 364 } 365 366 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) 367 { 368 uchar buffer[2]; 369 370 if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true)) 371 return 1; 372 373 return 0; 374 } 375 376 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 377 int alen, uchar *buffer, int len) 378 { 379 u8 addr_bytes[4]; 380 381 put_unaligned_le32(addr, addr_bytes); 382 383 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, 384 I2COP_READ); 385 } 386 387 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 388 int alen, uchar *buffer, int len) 389 { 390 u8 addr_bytes[4]; 391 392 put_unaligned_le32(addr, addr_bytes); 393 394 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, 395 I2COP_WRITE); 396 } 397 398 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, 399 unsigned int speed) 400 { 401 if (speed != adap->speed) 402 return 1; 403 return speed; 404 } 405 406 /* 407 * Register IHS i2c adapters 408 */ 409 #ifdef CONFIG_SYS_I2C_IHS_CH0 410 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, 411 ihs_i2c_read, ihs_i2c_write, 412 ihs_i2c_set_bus_speed, 413 CONFIG_SYS_I2C_IHS_SPEED_0, 414 CONFIG_SYS_I2C_IHS_SLAVE_0, 0) 415 #ifdef CONFIG_SYS_I2C_IHS_DUAL 416 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe, 417 ihs_i2c_read, ihs_i2c_write, 418 ihs_i2c_set_bus_speed, 419 CONFIG_SYS_I2C_IHS_SPEED_0_1, 420 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16) 421 #endif 422 #endif 423 #ifdef CONFIG_SYS_I2C_IHS_CH1 424 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, 425 ihs_i2c_read, ihs_i2c_write, 426 ihs_i2c_set_bus_speed, 427 CONFIG_SYS_I2C_IHS_SPEED_1, 428 CONFIG_SYS_I2C_IHS_SLAVE_1, 1) 429 #ifdef CONFIG_SYS_I2C_IHS_DUAL 430 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe, 431 ihs_i2c_read, ihs_i2c_write, 432 ihs_i2c_set_bus_speed, 433 CONFIG_SYS_I2C_IHS_SPEED_1_1, 434 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17) 435 #endif 436 #endif 437 #ifdef CONFIG_SYS_I2C_IHS_CH2 438 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, 439 ihs_i2c_read, ihs_i2c_write, 440 ihs_i2c_set_bus_speed, 441 CONFIG_SYS_I2C_IHS_SPEED_2, 442 CONFIG_SYS_I2C_IHS_SLAVE_2, 2) 443 #ifdef CONFIG_SYS_I2C_IHS_DUAL 444 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe, 445 ihs_i2c_read, ihs_i2c_write, 446 ihs_i2c_set_bus_speed, 447 CONFIG_SYS_I2C_IHS_SPEED_2_1, 448 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18) 449 #endif 450 #endif 451 #ifdef CONFIG_SYS_I2C_IHS_CH3 452 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, 453 ihs_i2c_read, ihs_i2c_write, 454 ihs_i2c_set_bus_speed, 455 CONFIG_SYS_I2C_IHS_SPEED_3, 456 CONFIG_SYS_I2C_IHS_SLAVE_3, 3) 457 #ifdef CONFIG_SYS_I2C_IHS_DUAL 458 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe, 459 ihs_i2c_read, ihs_i2c_write, 460 ihs_i2c_set_bus_speed, 461 CONFIG_SYS_I2C_IHS_SPEED_3_1, 462 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19) 463 #endif 464 #endif 465 #endif /* CONFIG_DM_I2C */ 466