1 /* 2 * (C) Copyright 2013 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <i2c.h> 10 #ifdef CONFIG_DM_I2C 11 #include <dm.h> 12 #include <fpgamap.h> 13 #include "../misc/gdsys_soc.h" 14 #else 15 #include <gdsys_fpga.h> 16 #endif 17 #include <asm/unaligned.h> 18 19 #ifdef CONFIG_DM_I2C 20 struct ihs_i2c_priv { 21 uint speed; 22 phys_addr_t addr; 23 }; 24 25 enum { 26 REG_INTERRUPT_STATUS = 0x00, 27 REG_INTERRUPT_ENABLE_CONTROL = 0x02, 28 REG_WRITE_MAILBOX_EXT = 0x04, 29 REG_WRITE_MAILBOX = 0x06, 30 REG_READ_MAILBOX_EXT = 0x08, 31 REG_READ_MAILBOX = 0x0A, 32 }; 33 34 #else /* !CONFIG_DM_I2C */ 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifdef CONFIG_SYS_I2C_IHS_DUAL 38 39 #define I2C_SET_REG(fld, val) \ 40 do { \ 41 if (I2C_ADAP_HWNR & 0x10) \ 42 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ 43 else \ 44 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ 45 } while (0) 46 #else 47 #define I2C_SET_REG(fld, val) \ 48 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val) 49 #endif 50 51 #ifdef CONFIG_SYS_I2C_IHS_DUAL 52 #define I2C_GET_REG(fld, val) \ 53 do { \ 54 if (I2C_ADAP_HWNR & 0x10) \ 55 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ 56 else \ 57 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ 58 } while (0) 59 #else 60 #define I2C_GET_REG(fld, val) \ 61 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val) 62 #endif 63 #endif /* CONFIG_DM_I2C */ 64 65 enum { 66 I2CINT_ERROR_EV = BIT(13), 67 I2CINT_TRANSMIT_EV = BIT(14), 68 I2CINT_RECEIVE_EV = BIT(15), 69 }; 70 71 enum { 72 I2CMB_READ = 0 << 10, 73 I2CMB_WRITE = 1 << 10, 74 I2CMB_1BYTE = 0 << 11, 75 I2CMB_2BYTE = 1 << 11, 76 I2CMB_DONT_HOLD_BUS = 0 << 13, 77 I2CMB_HOLD_BUS = 1 << 13, 78 I2CMB_NATIVE = 2 << 14, 79 }; 80 81 enum { 82 I2COP_WRITE = 0, 83 I2COP_READ = 1, 84 }; 85 86 #ifdef CONFIG_DM_I2C 87 static int wait_for_int(struct udevice *dev, int read) 88 #else 89 static int wait_for_int(bool read) 90 #endif 91 { 92 u16 val; 93 uint ctr = 0; 94 #ifdef CONFIG_DM_I2C 95 struct ihs_i2c_priv *priv = dev_get_priv(dev); 96 struct udevice *fpga; 97 98 gdsys_soc_get_fpga(dev, &fpga); 99 #endif 100 101 #ifdef CONFIG_DM_I2C 102 fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val); 103 #else 104 I2C_GET_REG(interrupt_status, &val); 105 #endif 106 /* Wait until error or receive/transmit interrupt was raised */ 107 while (!(val & (I2CINT_ERROR_EV 108 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { 109 udelay(10); 110 if (ctr++ > 5000) 111 return 1; 112 #ifdef CONFIG_DM_I2C 113 fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val); 114 #else 115 I2C_GET_REG(interrupt_status, &val); 116 #endif 117 } 118 119 return (val & I2CINT_ERROR_EV) ? 1 : 0; 120 } 121 122 #ifdef CONFIG_DM_I2C 123 static int ihs_i2c_transfer(struct udevice *dev, uchar chip, 124 uchar *buffer, int len, int read, bool is_last) 125 #else 126 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, 127 bool is_last) 128 #endif 129 { 130 u16 val; 131 #ifdef CONFIG_DM_I2C 132 struct ihs_i2c_priv *priv = dev_get_priv(dev); 133 struct udevice *fpga; 134 135 gdsys_soc_get_fpga(dev, &fpga); 136 #endif 137 138 /* Clear interrupt status */ 139 #ifdef CONFIG_DM_I2C 140 fpgamap_write16(fpga, priv->addr + REG_INTERRUPT_STATUS, 141 I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); 142 fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val); 143 #else 144 I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV 145 | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); 146 I2C_GET_REG(interrupt_status, &val); 147 #endif 148 149 /* If we want to write and have data, write the bytes to the mailbox */ 150 if (!read && len) { 151 val = buffer[0]; 152 153 if (len > 1) 154 val |= buffer[1] << 8; 155 #ifdef CONFIG_DM_I2C 156 fpgamap_write16(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, val); 157 #else 158 I2C_SET_REG(write_mailbox_ext, val); 159 #endif 160 } 161 162 #ifdef CONFIG_DM_I2C 163 fpgamap_write16(fpga, priv->addr + REG_WRITE_MAILBOX, 164 I2CMB_NATIVE 165 | (read ? I2CMB_READ : I2CMB_WRITE) 166 | (chip << 1) 167 | ((len > 1) ? I2CMB_2BYTE : I2CMB_1BYTE) 168 | (!is_last ? I2CMB_HOLD_BUS : I2CMB_DONT_HOLD_BUS)); 169 #else 170 I2C_SET_REG(write_mailbox, 171 I2CMB_NATIVE 172 | (read ? 0 : I2CMB_WRITE) 173 | (chip << 1) 174 | ((len > 1) ? I2CMB_2BYTE : 0) 175 | (is_last ? 0 : I2CMB_HOLD_BUS)); 176 #endif 177 178 #ifdef CONFIG_DM_I2C 179 if (wait_for_int(dev, read)) 180 #else 181 if (wait_for_int(read)) 182 #endif 183 return 1; 184 185 /* If we want to read, get the bytes from the mailbox */ 186 if (read) { 187 #ifdef CONFIG_DM_I2C 188 fpgamap_read16(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val); 189 #else 190 I2C_GET_REG(read_mailbox_ext, &val); 191 #endif 192 buffer[0] = val & 0xff; 193 if (len > 1) 194 buffer[1] = val >> 8; 195 } 196 197 return 0; 198 } 199 200 #ifdef CONFIG_DM_I2C 201 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read) 202 #else 203 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, 204 int read) 205 #endif 206 { 207 while (len) { 208 int transfer = min(len, 2); 209 bool is_last = len <= transfer; 210 211 #ifdef CONFIG_DM_I2C 212 if (ihs_i2c_transfer(dev, chip, data, transfer, read, 213 hold_bus ? false : is_last)) 214 return 1; 215 #else 216 if (ihs_i2c_transfer(chip, data, transfer, read, 217 hold_bus ? false : is_last)) 218 return 1; 219 #endif 220 221 data += transfer; 222 len -= transfer; 223 } 224 225 return 0; 226 } 227 228 #ifdef CONFIG_DM_I2C 229 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen, 230 bool hold_bus) 231 #else 232 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus) 233 #endif 234 { 235 #ifdef CONFIG_DM_I2C 236 return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE); 237 #else 238 return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE); 239 #endif 240 } 241 242 #ifdef CONFIG_DM_I2C 243 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr, 244 int alen, uchar *buffer, int len, int read) 245 #else 246 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, 247 int alen, uchar *buffer, int len, int read) 248 #endif 249 { 250 /* Don't hold the bus if length of data to send/receive is zero */ 251 #ifdef CONFIG_DM_I2C 252 if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len)) 253 return 1; 254 #else 255 if (len <= 0 || ihs_i2c_address(chip, addr, alen, len)) 256 return 1; 257 #endif 258 259 #ifdef CONFIG_DM_I2C 260 return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read); 261 #else 262 return ihs_i2c_send_buffer(chip, buffer, len, false, read); 263 #endif 264 } 265 266 #ifdef CONFIG_DM_I2C 267 268 int ihs_i2c_probe(struct udevice *bus) 269 { 270 struct ihs_i2c_priv *priv = dev_get_priv(bus); 271 int addr; 272 273 addr = dev_read_u32_default(bus, "reg", -1); 274 275 priv->addr = addr; 276 277 return 0; 278 } 279 280 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed) 281 { 282 struct ihs_i2c_priv *priv = dev_get_priv(bus); 283 284 if (speed != priv->speed && priv->speed != 0) 285 return 1; 286 287 priv->speed = speed; 288 289 return 0; 290 } 291 292 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 293 { 294 struct i2c_msg *dmsg, *omsg, dummy; 295 296 memset(&dummy, 0, sizeof(struct i2c_msg)); 297 298 /* We expect either two messages (one with an offset and one with the 299 * actucal data) or one message (just data) 300 */ 301 if (nmsgs > 2 || nmsgs == 0) { 302 debug("%s: Only one or two messages are supported.", __func__); 303 return -1; 304 } 305 306 omsg = nmsgs == 1 ? &dummy : msg; 307 dmsg = nmsgs == 1 ? msg : msg + 1; 308 309 if (dmsg->flags & I2C_M_RD) 310 return ihs_i2c_access(bus, dmsg->addr, omsg->buf, 311 omsg->len, dmsg->buf, dmsg->len, 312 I2COP_READ); 313 else 314 return ihs_i2c_access(bus, dmsg->addr, omsg->buf, 315 omsg->len, dmsg->buf, dmsg->len, 316 I2COP_WRITE); 317 } 318 319 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 320 u32 chip_flags) 321 { 322 uchar buffer[2]; 323 324 if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true)) 325 return 1; 326 327 return 0; 328 } 329 330 static const struct dm_i2c_ops ihs_i2c_ops = { 331 .xfer = ihs_i2c_xfer, 332 .probe_chip = ihs_i2c_probe_chip, 333 .set_bus_speed = ihs_i2c_set_bus_speed, 334 }; 335 336 static const struct udevice_id ihs_i2c_ids[] = { 337 { .compatible = "gdsys,ihs_i2cmaster", }, 338 { /* sentinel */ } 339 }; 340 341 U_BOOT_DRIVER(i2c_ihs) = { 342 .name = "i2c_ihs", 343 .id = UCLASS_I2C, 344 .of_match = ihs_i2c_ids, 345 .probe = ihs_i2c_probe, 346 .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv), 347 .ops = &ihs_i2c_ops, 348 }; 349 350 #else /* CONFIG_DM_I2C */ 351 352 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 353 { 354 #ifdef CONFIG_SYS_I2C_INIT_BOARD 355 /* 356 * Call board specific i2c bus reset routine before accessing the 357 * environment, which might be in a chip on that bus. For details 358 * about this problem see doc/I2C_Edge_Conditions. 359 */ 360 i2c_init_board(); 361 #endif 362 } 363 364 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) 365 { 366 uchar buffer[2]; 367 368 if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true)) 369 return 1; 370 371 return 0; 372 } 373 374 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 375 int alen, uchar *buffer, int len) 376 { 377 u8 addr_bytes[4]; 378 379 put_unaligned_le32(addr, addr_bytes); 380 381 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, 382 I2COP_READ); 383 } 384 385 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 386 int alen, uchar *buffer, int len) 387 { 388 u8 addr_bytes[4]; 389 390 put_unaligned_le32(addr, addr_bytes); 391 392 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, 393 I2COP_WRITE); 394 } 395 396 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, 397 unsigned int speed) 398 { 399 if (speed != adap->speed) 400 return 1; 401 return speed; 402 } 403 404 /* 405 * Register IHS i2c adapters 406 */ 407 #ifdef CONFIG_SYS_I2C_IHS_CH0 408 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, 409 ihs_i2c_read, ihs_i2c_write, 410 ihs_i2c_set_bus_speed, 411 CONFIG_SYS_I2C_IHS_SPEED_0, 412 CONFIG_SYS_I2C_IHS_SLAVE_0, 0) 413 #ifdef CONFIG_SYS_I2C_IHS_DUAL 414 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe, 415 ihs_i2c_read, ihs_i2c_write, 416 ihs_i2c_set_bus_speed, 417 CONFIG_SYS_I2C_IHS_SPEED_0_1, 418 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16) 419 #endif 420 #endif 421 #ifdef CONFIG_SYS_I2C_IHS_CH1 422 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, 423 ihs_i2c_read, ihs_i2c_write, 424 ihs_i2c_set_bus_speed, 425 CONFIG_SYS_I2C_IHS_SPEED_1, 426 CONFIG_SYS_I2C_IHS_SLAVE_1, 1) 427 #ifdef CONFIG_SYS_I2C_IHS_DUAL 428 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe, 429 ihs_i2c_read, ihs_i2c_write, 430 ihs_i2c_set_bus_speed, 431 CONFIG_SYS_I2C_IHS_SPEED_1_1, 432 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17) 433 #endif 434 #endif 435 #ifdef CONFIG_SYS_I2C_IHS_CH2 436 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, 437 ihs_i2c_read, ihs_i2c_write, 438 ihs_i2c_set_bus_speed, 439 CONFIG_SYS_I2C_IHS_SPEED_2, 440 CONFIG_SYS_I2C_IHS_SLAVE_2, 2) 441 #ifdef CONFIG_SYS_I2C_IHS_DUAL 442 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe, 443 ihs_i2c_read, ihs_i2c_write, 444 ihs_i2c_set_bus_speed, 445 CONFIG_SYS_I2C_IHS_SPEED_2_1, 446 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18) 447 #endif 448 #endif 449 #ifdef CONFIG_SYS_I2C_IHS_CH3 450 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, 451 ihs_i2c_read, ihs_i2c_write, 452 ihs_i2c_set_bus_speed, 453 CONFIG_SYS_I2C_IHS_SPEED_3, 454 CONFIG_SYS_I2C_IHS_SLAVE_3, 3) 455 #ifdef CONFIG_SYS_I2C_IHS_DUAL 456 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe, 457 ihs_i2c_read, ihs_i2c_write, 458 ihs_i2c_set_bus_speed, 459 CONFIG_SYS_I2C_IHS_SPEED_3_1, 460 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19) 461 #endif 462 #endif 463 #endif /* CONFIG_DM_I2C */ 464