1 /* 2 * Copyright (C) 2014 Panasonic Corporation 3 * Copyright (C) 2015 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <linux/types.h> 11 #include <asm/io.h> 12 #include <asm/errno.h> 13 #include <dm/device.h> 14 #include <dm/root.h> 15 #include <i2c.h> 16 #include <fdtdec.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 struct uniphier_i2c_regs { 21 u32 dtrm; /* data transmission */ 22 #define I2C_DTRM_STA (1 << 10) 23 #define I2C_DTRM_STO (1 << 9) 24 #define I2C_DTRM_NACK (1 << 8) 25 #define I2C_DTRM_RD (1 << 0) 26 u32 drec; /* data reception */ 27 #define I2C_DREC_STS (1 << 12) 28 #define I2C_DREC_LRB (1 << 11) 29 #define I2C_DREC_LAB (1 << 9) 30 u32 myad; /* slave address */ 31 u32 clk; /* clock frequency control */ 32 u32 brst; /* bus reset */ 33 #define I2C_BRST_FOEN (1 << 1) 34 #define I2C_BRST_BRST (1 << 0) 35 u32 hold; /* hold time control */ 36 u32 bsts; /* bus status monitor */ 37 u32 noise; /* noise filter control */ 38 u32 setup; /* setup time control */ 39 }; 40 41 #define IOBUS_FREQ 100000000 42 43 struct uniphier_i2c_dev { 44 struct uniphier_i2c_regs __iomem *regs; /* register base */ 45 unsigned long input_clk; /* master clock (Hz) */ 46 unsigned long wait_us; /* wait for every byte transfer (us) */ 47 }; 48 49 static int uniphier_i2c_probe(struct udevice *dev) 50 { 51 fdt_addr_t addr; 52 fdt_size_t size; 53 struct uniphier_i2c_dev *priv = dev_get_priv(dev); 54 55 addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); 56 57 priv->regs = map_sysmem(addr, size); 58 59 if (!priv->regs) 60 return -ENOMEM; 61 62 priv->input_clk = IOBUS_FREQ; 63 64 /* deassert reset */ 65 writel(0x3, &priv->regs->brst); 66 67 return 0; 68 } 69 70 static int uniphier_i2c_remove(struct udevice *dev) 71 { 72 struct uniphier_i2c_dev *priv = dev_get_priv(dev); 73 74 unmap_sysmem(priv->regs); 75 76 return 0; 77 } 78 79 static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm) 80 { 81 writel(dtrm, &dev->regs->dtrm); 82 83 /* 84 * This controller only provides interruption to inform the completion 85 * of each byte transfer. (No status register to poll it.) 86 * Unfortunately, U-Boot does not have a good support of interrupt. 87 * Wait for a while. 88 */ 89 udelay(dev->wait_us); 90 91 return readl(&dev->regs->drec); 92 } 93 94 static int send_byte(struct uniphier_i2c_dev *dev, u32 dtrm, bool *stop) 95 { 96 int ret = 0; 97 u32 drec; 98 99 drec = send_and_recv_byte(dev, dtrm); 100 101 if (drec & I2C_DREC_LAB) { 102 debug("uniphier_i2c: bus arbitration failed\n"); 103 *stop = false; 104 ret = -EREMOTEIO; 105 } 106 if (drec & I2C_DREC_LRB) { 107 debug("uniphier_i2c: slave did not return ACK\n"); 108 ret = -EREMOTEIO; 109 } 110 return ret; 111 } 112 113 static int uniphier_i2c_transmit(struct uniphier_i2c_dev *dev, uint addr, 114 uint len, const u8 *buf, bool *stop) 115 { 116 int ret; 117 118 debug("%s: addr = %x, len = %d\n", __func__, addr, len); 119 120 ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop); 121 if (ret < 0) 122 goto fail; 123 124 while (len--) { 125 ret = send_byte(dev, I2C_DTRM_NACK | *buf++, stop); 126 if (ret < 0) 127 goto fail; 128 } 129 130 fail: 131 if (*stop) 132 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); 133 134 return ret; 135 } 136 137 static int uniphier_i2c_receive(struct uniphier_i2c_dev *dev, uint addr, 138 uint len, u8 *buf, bool *stop) 139 { 140 int ret; 141 142 debug("%s: addr = %x, len = %d\n", __func__, addr, len); 143 144 ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | 145 I2C_DTRM_RD | addr << 1, stop); 146 if (ret < 0) 147 goto fail; 148 149 while (len--) 150 *buf++ = send_and_recv_byte(dev, len ? 0 : I2C_DTRM_NACK); 151 152 fail: 153 if (*stop) 154 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); 155 156 return ret; 157 } 158 159 static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 160 int nmsgs) 161 { 162 int ret = 0; 163 struct uniphier_i2c_dev *dev = dev_get_priv(bus); 164 bool stop; 165 166 for (; nmsgs > 0; nmsgs--, msg++) { 167 /* If next message is read, skip the stop condition */ 168 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true; 169 170 if (msg->flags & I2C_M_RD) 171 ret = uniphier_i2c_receive(dev, msg->addr, msg->len, 172 msg->buf, &stop); 173 else 174 ret = uniphier_i2c_transmit(dev, msg->addr, msg->len, 175 msg->buf, &stop); 176 177 if (ret < 0) 178 break; 179 } 180 181 return ret; 182 } 183 184 static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 185 { 186 struct uniphier_i2c_dev *priv = dev_get_priv(bus); 187 188 /* max supported frequency is 400 kHz */ 189 if (speed > 400000) 190 return -EINVAL; 191 192 /* bus reset: make sure the bus is idle when change the frequency */ 193 writel(0x1, &priv->regs->brst); 194 195 writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed), 196 &priv->regs->clk); 197 198 writel(0x3, &priv->regs->brst); 199 200 /* 201 * Theoretically, each byte can be transferred in 202 * 1000000 * 9 / speed usec. For safety, wait more than double. 203 */ 204 priv->wait_us = 20000000 / speed; 205 206 return 0; 207 } 208 209 210 static const struct dm_i2c_ops uniphier_i2c_ops = { 211 .xfer = uniphier_i2c_xfer, 212 .set_bus_speed = uniphier_i2c_set_bus_speed, 213 }; 214 215 static const struct udevice_id uniphier_i2c_of_match[] = { 216 { .compatible = "socionext,uniphier-i2c" }, 217 { /* sentinel */ } 218 }; 219 220 U_BOOT_DRIVER(uniphier_i2c) = { 221 .name = "uniphier-i2c", 222 .id = UCLASS_I2C, 223 .of_match = uniphier_i2c_of_match, 224 .probe = uniphier_i2c_probe, 225 .remove = uniphier_i2c_remove, 226 .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev), 227 .ops = &uniphier_i2c_ops, 228 }; 229