1 /* 2 * Copyright (C) 2014 Panasonic Corporation 3 * Copyright (C) 2015 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <linux/types.h> 11 #include <asm/io.h> 12 #include <asm/errno.h> 13 #include <dm/device.h> 14 #include <dm/root.h> 15 #include <i2c.h> 16 #include <fdtdec.h> 17 #include <mapmem.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 struct uniphier_i2c_regs { 22 u32 dtrm; /* data transmission */ 23 #define I2C_DTRM_STA (1 << 10) 24 #define I2C_DTRM_STO (1 << 9) 25 #define I2C_DTRM_NACK (1 << 8) 26 #define I2C_DTRM_RD (1 << 0) 27 u32 drec; /* data reception */ 28 #define I2C_DREC_STS (1 << 12) 29 #define I2C_DREC_LRB (1 << 11) 30 #define I2C_DREC_LAB (1 << 9) 31 u32 myad; /* slave address */ 32 u32 clk; /* clock frequency control */ 33 u32 brst; /* bus reset */ 34 #define I2C_BRST_FOEN (1 << 1) 35 #define I2C_BRST_BRST (1 << 0) 36 u32 hold; /* hold time control */ 37 u32 bsts; /* bus status monitor */ 38 u32 noise; /* noise filter control */ 39 u32 setup; /* setup time control */ 40 }; 41 42 #define IOBUS_FREQ 100000000 43 44 struct uniphier_i2c_dev { 45 struct uniphier_i2c_regs __iomem *regs; /* register base */ 46 unsigned long input_clk; /* master clock (Hz) */ 47 unsigned long wait_us; /* wait for every byte transfer (us) */ 48 }; 49 50 static int uniphier_i2c_probe(struct udevice *dev) 51 { 52 fdt_addr_t addr; 53 fdt_size_t size; 54 struct uniphier_i2c_dev *priv = dev_get_priv(dev); 55 56 addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); 57 58 priv->regs = map_sysmem(addr, size); 59 60 if (!priv->regs) 61 return -ENOMEM; 62 63 priv->input_clk = IOBUS_FREQ; 64 65 /* deassert reset */ 66 writel(0x3, &priv->regs->brst); 67 68 return 0; 69 } 70 71 static int uniphier_i2c_remove(struct udevice *dev) 72 { 73 struct uniphier_i2c_dev *priv = dev_get_priv(dev); 74 75 unmap_sysmem(priv->regs); 76 77 return 0; 78 } 79 80 static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm) 81 { 82 writel(dtrm, &dev->regs->dtrm); 83 84 /* 85 * This controller only provides interruption to inform the completion 86 * of each byte transfer. (No status register to poll it.) 87 * Unfortunately, U-Boot does not have a good support of interrupt. 88 * Wait for a while. 89 */ 90 udelay(dev->wait_us); 91 92 return readl(&dev->regs->drec); 93 } 94 95 static int send_byte(struct uniphier_i2c_dev *dev, u32 dtrm, bool *stop) 96 { 97 int ret = 0; 98 u32 drec; 99 100 drec = send_and_recv_byte(dev, dtrm); 101 102 if (drec & I2C_DREC_LAB) { 103 debug("uniphier_i2c: bus arbitration failed\n"); 104 *stop = false; 105 ret = -EREMOTEIO; 106 } 107 if (drec & I2C_DREC_LRB) { 108 debug("uniphier_i2c: slave did not return ACK\n"); 109 ret = -EREMOTEIO; 110 } 111 return ret; 112 } 113 114 static int uniphier_i2c_transmit(struct uniphier_i2c_dev *dev, uint addr, 115 uint len, const u8 *buf, bool *stop) 116 { 117 int ret; 118 119 debug("%s: addr = %x, len = %d\n", __func__, addr, len); 120 121 ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop); 122 if (ret < 0) 123 goto fail; 124 125 while (len--) { 126 ret = send_byte(dev, I2C_DTRM_NACK | *buf++, stop); 127 if (ret < 0) 128 goto fail; 129 } 130 131 fail: 132 if (*stop) 133 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); 134 135 return ret; 136 } 137 138 static int uniphier_i2c_receive(struct uniphier_i2c_dev *dev, uint addr, 139 uint len, u8 *buf, bool *stop) 140 { 141 int ret; 142 143 debug("%s: addr = %x, len = %d\n", __func__, addr, len); 144 145 ret = send_byte(dev, I2C_DTRM_STA | I2C_DTRM_NACK | 146 I2C_DTRM_RD | addr << 1, stop); 147 if (ret < 0) 148 goto fail; 149 150 while (len--) 151 *buf++ = send_and_recv_byte(dev, len ? 0 : I2C_DTRM_NACK); 152 153 fail: 154 if (*stop) 155 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &dev->regs->dtrm); 156 157 return ret; 158 } 159 160 static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 161 int nmsgs) 162 { 163 int ret = 0; 164 struct uniphier_i2c_dev *dev = dev_get_priv(bus); 165 bool stop; 166 167 for (; nmsgs > 0; nmsgs--, msg++) { 168 /* If next message is read, skip the stop condition */ 169 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true; 170 171 if (msg->flags & I2C_M_RD) 172 ret = uniphier_i2c_receive(dev, msg->addr, msg->len, 173 msg->buf, &stop); 174 else 175 ret = uniphier_i2c_transmit(dev, msg->addr, msg->len, 176 msg->buf, &stop); 177 178 if (ret < 0) 179 break; 180 } 181 182 return ret; 183 } 184 185 static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 186 { 187 struct uniphier_i2c_dev *priv = dev_get_priv(bus); 188 189 /* max supported frequency is 400 kHz */ 190 if (speed > 400000) 191 return -EINVAL; 192 193 /* bus reset: make sure the bus is idle when change the frequency */ 194 writel(0x1, &priv->regs->brst); 195 196 writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed), 197 &priv->regs->clk); 198 199 writel(0x3, &priv->regs->brst); 200 201 /* 202 * Theoretically, each byte can be transferred in 203 * 1000000 * 9 / speed usec. For safety, wait more than double. 204 */ 205 priv->wait_us = 20000000 / speed; 206 207 return 0; 208 } 209 210 211 static const struct dm_i2c_ops uniphier_i2c_ops = { 212 .xfer = uniphier_i2c_xfer, 213 .set_bus_speed = uniphier_i2c_set_bus_speed, 214 }; 215 216 static const struct udevice_id uniphier_i2c_of_match[] = { 217 { .compatible = "socionext,uniphier-i2c" }, 218 { /* sentinel */ } 219 }; 220 221 U_BOOT_DRIVER(uniphier_i2c) = { 222 .name = "uniphier-i2c", 223 .id = UCLASS_I2C, 224 .of_match = uniphier_i2c_of_match, 225 .probe = uniphier_i2c_probe, 226 .remove = uniphier_i2c_remove, 227 .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev), 228 .ops = &uniphier_i2c_ops, 229 }; 230