1 /* 2 * Copyright (C) 2014 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/sizes.h> 13 #include <linux/types.h> 14 #include <dm.h> 15 #include <i2c.h> 16 #include <fdtdec.h> 17 18 struct uniphier_fi2c_regs { 19 u32 cr; /* control register */ 20 #define I2C_CR_MST (1 << 3) /* master mode */ 21 #define I2C_CR_STA (1 << 2) /* start condition */ 22 #define I2C_CR_STO (1 << 1) /* stop condition */ 23 #define I2C_CR_NACK (1 << 0) /* not ACK */ 24 u32 dttx; /* send FIFO (write-only) */ 25 #define dtrx dttx /* receive FIFO (read-only) */ 26 #define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */ 27 #define I2C_DTTX_RD (1 << 0) /* read */ 28 u32 __reserved; /* no register at offset 0x08 */ 29 u32 slad; /* slave address */ 30 u32 cyc; /* clock cycle control */ 31 u32 lctl; /* clock low period control */ 32 u32 ssut; /* restart/stop setup time control */ 33 u32 dsut; /* data setup time control */ 34 u32 intr; /* interrupt status */ 35 u32 ie; /* interrupt enable */ 36 u32 ic; /* interrupt clear */ 37 #define I2C_INT_TE (1 << 9) /* TX FIFO empty */ 38 #define I2C_INT_RB (1 << 4) /* received specified bytes */ 39 #define I2C_INT_NA (1 << 2) /* no answer */ 40 #define I2C_INT_AL (1 << 1) /* arbitration lost */ 41 u32 sr; /* status register */ 42 #define I2C_SR_DB (1 << 12) /* device busy */ 43 #define I2C_SR_BB (1 << 8) /* bus busy */ 44 #define I2C_SR_RFF (1 << 3) /* Rx FIFO full */ 45 #define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */ 46 #define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */ 47 #define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */ 48 u32 __reserved2; /* no register at offset 0x30 */ 49 u32 rst; /* reset control */ 50 #define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */ 51 #define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */ 52 #define I2C_RST_RST (1 << 0) /* forcible bus reset */ 53 u32 bm; /* bus monitor */ 54 u32 noise; /* noise filter control */ 55 u32 tbc; /* Tx byte count setting */ 56 u32 rbc; /* Rx byte count setting */ 57 u32 tbcm; /* Tx byte count monitor */ 58 u32 rbcm; /* Rx byte count monitor */ 59 u32 brst; /* bus reset */ 60 #define I2C_BRST_FOEN (1 << 1) /* normal operation */ 61 #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */ 62 }; 63 64 #define FIOCLK 50000000 65 66 struct uniphier_fi2c_priv { 67 struct udevice *dev; 68 struct uniphier_fi2c_regs __iomem *regs; /* register base */ 69 unsigned long fioclk; /* internal operation clock */ 70 unsigned long timeout; /* time out (us) */ 71 }; 72 73 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv) 74 { 75 writel(I2C_RST_RST, &priv->regs->rst); 76 } 77 78 static int uniphier_fi2c_check_bus_busy(struct uniphier_fi2c_priv *priv) 79 { 80 u32 val; 81 int ret; 82 83 ret = readl_poll_timeout(&priv->regs->sr, val, !(val & I2C_SR_DB), 100); 84 if (ret < 0) { 85 dev_dbg(priv->dev, "error: device busy too long. reset...\n"); 86 uniphier_fi2c_reset(priv); 87 } 88 89 return ret; 90 } 91 92 static int uniphier_fi2c_probe(struct udevice *dev) 93 { 94 fdt_addr_t addr; 95 struct uniphier_fi2c_priv *priv = dev_get_priv(dev); 96 97 addr = devfdt_get_addr(dev); 98 if (addr == FDT_ADDR_T_NONE) 99 return -EINVAL; 100 101 priv->regs = devm_ioremap(dev, addr, SZ_128); 102 if (!priv->regs) 103 return -ENOMEM; 104 105 priv->fioclk = FIOCLK; 106 107 priv->dev = dev; 108 109 /* bus forcible reset */ 110 uniphier_fi2c_reset(priv); 111 112 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst); 113 114 return 0; 115 } 116 117 static int wait_for_irq(struct uniphier_fi2c_priv *priv, u32 flags, 118 bool *stop) 119 { 120 u32 irq; 121 int ret; 122 123 ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags, 124 priv->timeout); 125 if (ret < 0) { 126 dev_dbg(priv->dev, "error: time out\n"); 127 return ret; 128 } 129 130 if (irq & I2C_INT_AL) { 131 dev_dbg(priv->dev, "error: arbitration lost\n"); 132 *stop = false; 133 return ret; 134 } 135 136 if (irq & I2C_INT_NA) { 137 dev_dbg(priv->dev, "error: no answer\n"); 138 return ret; 139 } 140 141 return 0; 142 } 143 144 static int issue_stop(struct uniphier_fi2c_priv *priv, int old_ret) 145 { 146 int ret; 147 148 dev_dbg(priv->dev, "stop condition\n"); 149 writel(I2C_CR_MST | I2C_CR_STO, &priv->regs->cr); 150 151 ret = uniphier_fi2c_check_bus_busy(priv); 152 if (ret < 0) 153 dev_dbg(priv->dev, "error: device busy after operation\n"); 154 155 return old_ret ? old_ret : ret; 156 } 157 158 static int uniphier_fi2c_transmit(struct uniphier_fi2c_priv *priv, uint addr, 159 uint len, const u8 *buf, bool *stop) 160 { 161 int ret; 162 const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL; 163 struct uniphier_fi2c_regs __iomem *regs = priv->regs; 164 165 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len); 166 167 writel(I2C_DTTX_CMD | addr << 1, ®s->dttx); 168 169 writel(irq_flags, ®s->ie); 170 writel(irq_flags, ®s->ic); 171 172 dev_dbg(priv->dev, "start condition\n"); 173 writel(I2C_CR_MST | I2C_CR_STA, ®s->cr); 174 175 ret = wait_for_irq(priv, irq_flags, stop); 176 if (ret < 0) 177 goto error; 178 179 while (len--) { 180 dev_dbg(priv->dev, "sending %x\n", *buf); 181 writel(*buf++, ®s->dttx); 182 183 writel(irq_flags, ®s->ic); 184 185 ret = wait_for_irq(priv, irq_flags, stop); 186 if (ret < 0) 187 goto error; 188 } 189 190 error: 191 writel(irq_flags, ®s->ic); 192 193 if (*stop) 194 ret = issue_stop(priv, ret); 195 196 return ret; 197 } 198 199 static int uniphier_fi2c_receive(struct uniphier_fi2c_priv *priv, uint addr, 200 uint len, u8 *buf, bool *stop) 201 { 202 int ret = 0; 203 const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL; 204 struct uniphier_fi2c_regs __iomem *regs = priv->regs; 205 206 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len); 207 208 /* 209 * In case 'len == 0', only the slave address should be sent 210 * for probing, which is covered by the transmit function. 211 */ 212 if (len == 0) 213 return uniphier_fi2c_transmit(priv, addr, len, buf, stop); 214 215 writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, ®s->dttx); 216 217 writel(0, ®s->rbc); 218 writel(irq_flags, ®s->ie); 219 writel(irq_flags, ®s->ic); 220 221 dev_dbg(priv->dev, "start condition\n"); 222 writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0), 223 ®s->cr); 224 225 while (len--) { 226 ret = wait_for_irq(priv, irq_flags, stop); 227 if (ret < 0) 228 goto error; 229 230 *buf++ = readl(®s->dtrx); 231 dev_dbg(priv->dev, "received %x\n", *(buf - 1)); 232 233 if (len == 1) 234 writel(I2C_CR_MST | I2C_CR_NACK, ®s->cr); 235 236 writel(irq_flags, ®s->ic); 237 } 238 239 error: 240 writel(irq_flags, ®s->ic); 241 242 if (*stop) 243 ret = issue_stop(priv, ret); 244 245 return ret; 246 } 247 248 static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg, 249 int nmsgs) 250 { 251 int ret; 252 struct uniphier_fi2c_priv *priv = dev_get_priv(bus); 253 bool stop; 254 255 ret = uniphier_fi2c_check_bus_busy(priv); 256 if (ret < 0) 257 return ret; 258 259 for (; nmsgs > 0; nmsgs--, msg++) { 260 /* If next message is read, skip the stop condition */ 261 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true; 262 263 if (msg->flags & I2C_M_RD) 264 ret = uniphier_fi2c_receive(priv, msg->addr, msg->len, 265 msg->buf, &stop); 266 else 267 ret = uniphier_fi2c_transmit(priv, msg->addr, msg->len, 268 msg->buf, &stop); 269 270 if (ret < 0) 271 break; 272 } 273 274 return ret; 275 } 276 277 static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed) 278 { 279 int ret; 280 unsigned int clk_count; 281 struct uniphier_fi2c_priv *priv = dev_get_priv(bus); 282 struct uniphier_fi2c_regs __iomem *regs = priv->regs; 283 284 /* max supported frequency is 400 kHz */ 285 if (speed > 400000) 286 return -EINVAL; 287 288 ret = uniphier_fi2c_check_bus_busy(priv); 289 if (ret < 0) 290 return ret; 291 292 /* make sure the bus is idle when changing the frequency */ 293 writel(I2C_BRST_RSCLO, ®s->brst); 294 295 clk_count = priv->fioclk / speed; 296 297 writel(clk_count, ®s->cyc); 298 writel(clk_count / 2, ®s->lctl); 299 writel(clk_count / 2, ®s->ssut); 300 writel(clk_count / 16, ®s->dsut); 301 302 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, ®s->brst); 303 304 /* 305 * Theoretically, each byte can be transferred in 306 * 1000000 * 9 / speed usec. 307 * This time out value is long enough. 308 */ 309 priv->timeout = 100000000L / speed; 310 311 return 0; 312 } 313 314 static const struct dm_i2c_ops uniphier_fi2c_ops = { 315 .xfer = uniphier_fi2c_xfer, 316 .set_bus_speed = uniphier_fi2c_set_bus_speed, 317 }; 318 319 static const struct udevice_id uniphier_fi2c_of_match[] = { 320 { .compatible = "socionext,uniphier-fi2c" }, 321 { /* sentinel */ } 322 }; 323 324 U_BOOT_DRIVER(uniphier_fi2c) = { 325 .name = "uniphier-fi2c", 326 .id = UCLASS_I2C, 327 .of_match = uniphier_fi2c_of_match, 328 .probe = uniphier_fi2c_probe, 329 .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_priv), 330 .ops = &uniphier_fi2c_ops, 331 }; 332