1 /* 2 * Copyright (C) 2014 Panasonic Corporation 3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <linux/types.h> 10 #include <asm/io.h> 11 #include <asm/errno.h> 12 #include <dm/device.h> 13 #include <dm/root.h> 14 #include <i2c.h> 15 #include <fdtdec.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 struct uniphier_fi2c_regs { 20 u32 cr; /* control register */ 21 #define I2C_CR_MST (1 << 3) /* master mode */ 22 #define I2C_CR_STA (1 << 2) /* start condition */ 23 #define I2C_CR_STO (1 << 1) /* stop condition */ 24 #define I2C_CR_NACK (1 << 0) /* not ACK */ 25 u32 dttx; /* send FIFO (write-only) */ 26 #define dtrx dttx /* receive FIFO (read-only) */ 27 #define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */ 28 #define I2C_DTTX_RD (1 << 0) /* read */ 29 u32 __reserved; /* no register at offset 0x08 */ 30 u32 slad; /* slave address */ 31 u32 cyc; /* clock cycle control */ 32 u32 lctl; /* clock low period control */ 33 u32 ssut; /* restart/stop setup time control */ 34 u32 dsut; /* data setup time control */ 35 u32 intr; /* interrupt status */ 36 u32 ie; /* interrupt enable */ 37 u32 ic; /* interrupt clear */ 38 #define I2C_INT_TE (1 << 9) /* TX FIFO empty */ 39 #define I2C_INT_RB (1 << 4) /* received specified bytes */ 40 #define I2C_INT_NA (1 << 2) /* no answer */ 41 #define I2C_INT_AL (1 << 1) /* arbitration lost */ 42 u32 sr; /* status register */ 43 #define I2C_SR_DB (1 << 12) /* device busy */ 44 #define I2C_SR_BB (1 << 8) /* bus busy */ 45 #define I2C_SR_RFF (1 << 3) /* Rx FIFO full */ 46 #define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */ 47 #define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */ 48 #define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */ 49 u32 __reserved2; /* no register at offset 0x30 */ 50 u32 rst; /* reset control */ 51 #define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */ 52 #define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */ 53 #define I2C_RST_RST (1 << 0) /* forcible bus reset */ 54 u32 bm; /* bus monitor */ 55 u32 noise; /* noise filter control */ 56 u32 tbc; /* Tx byte count setting */ 57 u32 rbc; /* Rx byte count setting */ 58 u32 tbcm; /* Tx byte count monitor */ 59 u32 rbcm; /* Rx byte count monitor */ 60 u32 brst; /* bus reset */ 61 #define I2C_BRST_FOEN (1 << 1) /* normal operation */ 62 #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */ 63 }; 64 65 #define FIOCLK 50000000 66 67 struct uniphier_fi2c_dev { 68 struct uniphier_fi2c_regs __iomem *regs; /* register base */ 69 unsigned long fioclk; /* internal operation clock */ 70 unsigned long timeout; /* time out (us) */ 71 }; 72 73 static int poll_status(u32 __iomem *reg, u32 flag) 74 { 75 int wait = 1000000; /* 1 sec is long enough */ 76 77 while (readl(reg) & flag) { 78 if (wait-- < 0) 79 return -EREMOTEIO; 80 udelay(1); 81 } 82 83 return 0; 84 } 85 86 static int reset_bus(struct uniphier_fi2c_regs __iomem *regs) 87 { 88 int ret; 89 90 /* bus forcible reset */ 91 writel(I2C_RST_RST, ®s->rst); 92 ret = poll_status(®s->rst, I2C_RST_RST); 93 if (ret < 0) 94 debug("error: fail to reset I2C controller\n"); 95 96 return ret; 97 } 98 99 static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs) 100 { 101 int ret; 102 103 ret = poll_status(®s->sr, I2C_SR_DB); 104 if (ret < 0) { 105 debug("error: device busy too long. reset...\n"); 106 ret = reset_bus(regs); 107 } 108 109 return ret; 110 } 111 112 static int uniphier_fi2c_probe(struct udevice *dev) 113 { 114 fdt_addr_t addr; 115 fdt_size_t size; 116 struct uniphier_fi2c_dev *priv = dev_get_priv(dev); 117 int ret; 118 119 addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", 120 &size); 121 122 priv->regs = map_sysmem(addr, size); 123 124 if (!priv->regs) 125 return -ENOMEM; 126 127 priv->fioclk = FIOCLK; 128 129 /* bus forcible reset */ 130 ret = reset_bus(priv->regs); 131 if (ret < 0) 132 return ret; 133 134 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst); 135 136 return 0; 137 } 138 139 static int uniphier_fi2c_remove(struct udevice *dev) 140 { 141 struct uniphier_fi2c_dev *priv = dev_get_priv(dev); 142 143 unmap_sysmem(priv->regs); 144 145 return 0; 146 } 147 148 static int uniphier_fi2c_child_pre_probe(struct udevice *dev) 149 { 150 struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev); 151 152 if (dev->of_offset == -1) 153 return 0; 154 return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, 155 i2c_chip); 156 } 157 158 static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags, 159 bool *stop) 160 { 161 u32 irq; 162 unsigned long wait = dev->timeout; 163 int ret = -EREMOTEIO; 164 165 do { 166 udelay(1); 167 irq = readl(&dev->regs->intr); 168 } while (!(irq & flags) && wait--); 169 170 if (wait < 0) { 171 debug("error: time out\n"); 172 return ret; 173 } 174 175 if (irq & I2C_INT_AL) { 176 debug("error: arbitration lost\n"); 177 *stop = false; 178 return ret; 179 } 180 181 if (irq & I2C_INT_NA) { 182 debug("error: no answer\n"); 183 return ret; 184 } 185 186 return 0; 187 } 188 189 static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret) 190 { 191 int ret; 192 193 debug("stop condition\n"); 194 writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr); 195 196 ret = poll_status(&dev->regs->sr, I2C_SR_DB); 197 if (ret < 0) 198 debug("error: device busy after operation\n"); 199 200 return old_ret ? old_ret : ret; 201 } 202 203 static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr, 204 uint len, const u8 *buf, bool *stop) 205 { 206 int ret; 207 const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL; 208 struct uniphier_fi2c_regs __iomem *regs = dev->regs; 209 210 debug("%s: addr = %x, len = %d\n", __func__, addr, len); 211 212 writel(I2C_DTTX_CMD | addr << 1, ®s->dttx); 213 214 writel(irq_flags, ®s->ie); 215 writel(irq_flags, ®s->ic); 216 217 debug("start condition\n"); 218 writel(I2C_CR_MST | I2C_CR_STA, ®s->cr); 219 220 ret = wait_for_irq(dev, irq_flags, stop); 221 if (ret < 0) 222 goto error; 223 224 while (len--) { 225 debug("sending %x\n", *buf); 226 writel(*buf++, ®s->dttx); 227 228 writel(irq_flags, ®s->ic); 229 230 ret = wait_for_irq(dev, irq_flags, stop); 231 if (ret < 0) 232 goto error; 233 } 234 235 error: 236 writel(irq_flags, ®s->ic); 237 238 if (*stop) 239 ret = issue_stop(dev, ret); 240 241 return ret; 242 } 243 244 static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr, 245 uint len, u8 *buf, bool *stop) 246 { 247 int ret = 0; 248 const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL; 249 struct uniphier_fi2c_regs __iomem *regs = dev->regs; 250 251 debug("%s: addr = %x, len = %d\n", __func__, addr, len); 252 253 /* 254 * In case 'len == 0', only the slave address should be sent 255 * for probing, which is covered by the transmit function. 256 */ 257 if (len == 0) 258 return uniphier_fi2c_transmit(dev, addr, len, buf, stop); 259 260 writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, ®s->dttx); 261 262 writel(0, ®s->rbc); 263 writel(irq_flags, ®s->ie); 264 writel(irq_flags, ®s->ic); 265 266 debug("start condition\n"); 267 writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0), 268 ®s->cr); 269 270 while (len--) { 271 ret = wait_for_irq(dev, irq_flags, stop); 272 if (ret < 0) 273 goto error; 274 275 *buf++ = readl(®s->dtrx); 276 debug("received %x\n", *(buf - 1)); 277 278 if (len == 1) 279 writel(I2C_CR_MST | I2C_CR_NACK, ®s->cr); 280 281 writel(irq_flags, ®s->ic); 282 } 283 284 error: 285 writel(irq_flags, ®s->ic); 286 287 if (*stop) 288 ret = issue_stop(dev, ret); 289 290 return ret; 291 } 292 293 static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg, 294 int nmsgs) 295 { 296 int ret; 297 struct uniphier_fi2c_dev *dev = dev_get_priv(bus); 298 bool stop; 299 300 ret = check_device_busy(dev->regs); 301 if (ret < 0) 302 return ret; 303 304 for (; nmsgs > 0; nmsgs--, msg++) { 305 /* If next message is read, skip the stop condition */ 306 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true; 307 308 if (msg->flags & I2C_M_RD) 309 ret = uniphier_fi2c_receive(dev, msg->addr, msg->len, 310 msg->buf, &stop); 311 else 312 ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len, 313 msg->buf, &stop); 314 315 if (ret < 0) 316 break; 317 } 318 319 return ret; 320 } 321 322 static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed) 323 { 324 int ret; 325 unsigned int clk_count; 326 struct uniphier_fi2c_dev *dev = dev_get_priv(bus); 327 struct uniphier_fi2c_regs __iomem *regs = dev->regs; 328 329 /* max supported frequency is 400 kHz */ 330 if (speed > 400000) 331 return -EINVAL; 332 333 ret = check_device_busy(dev->regs); 334 if (ret < 0) 335 return ret; 336 337 /* make sure the bus is idle when changing the frequency */ 338 writel(I2C_BRST_RSCLO, ®s->brst); 339 340 clk_count = dev->fioclk / speed; 341 342 writel(clk_count, ®s->cyc); 343 writel(clk_count / 2, ®s->lctl); 344 writel(clk_count / 2, ®s->ssut); 345 writel(clk_count / 16, ®s->dsut); 346 347 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, ®s->brst); 348 349 /* 350 * Theoretically, each byte can be transferred in 351 * 1000000 * 9 / speed usec. 352 * This time out value is long enough. 353 */ 354 dev->timeout = 100000000L / speed; 355 356 return 0; 357 } 358 359 static const struct dm_i2c_ops uniphier_fi2c_ops = { 360 .xfer = uniphier_fi2c_xfer, 361 .set_bus_speed = uniphier_fi2c_set_bus_speed, 362 }; 363 364 static const struct udevice_id uniphier_fi2c_of_match[] = { 365 { .compatible = "panasonic,uniphier-fi2c" }, 366 {}, 367 }; 368 369 U_BOOT_DRIVER(uniphier_fi2c) = { 370 .name = "uniphier-fi2c", 371 .id = UCLASS_I2C, 372 .of_match = uniphier_fi2c_of_match, 373 .probe = uniphier_fi2c_probe, 374 .remove = uniphier_fi2c_remove, 375 .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), 376 .child_pre_probe = uniphier_fi2c_child_pre_probe, 377 .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev), 378 .ops = &uniphier_fi2c_ops, 379 }; 380