1 /* 2 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com> 3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) 4 * 5 * This file is based on: drivers/i2c/zynq_i2c.c, 6 * with added driver-model support and code cleanup. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <linux/types.h> 13 #include <linux/io.h> 14 #include <asm/errno.h> 15 #include <dm/device.h> 16 #include <dm/root.h> 17 #include <i2c.h> 18 #include <fdtdec.h> 19 #include <mapmem.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* i2c register set */ 24 struct cdns_i2c_regs { 25 u32 control; 26 u32 status; 27 u32 address; 28 u32 data; 29 u32 interrupt_status; 30 u32 transfer_size; 31 u32 slave_mon_pause; 32 u32 time_out; 33 u32 interrupt_mask; 34 u32 interrupt_enable; 35 u32 interrupt_disable; 36 }; 37 38 /* Control register fields */ 39 #define CDNS_I2C_CONTROL_RW 0x00000001 40 #define CDNS_I2C_CONTROL_MS 0x00000002 41 #define CDNS_I2C_CONTROL_NEA 0x00000004 42 #define CDNS_I2C_CONTROL_ACKEN 0x00000008 43 #define CDNS_I2C_CONTROL_HOLD 0x00000010 44 #define CDNS_I2C_CONTROL_SLVMON 0x00000020 45 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 47 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 49 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 50 51 /* Status register values */ 52 #define CDNS_I2C_STATUS_RXDV 0x00000020 53 #define CDNS_I2C_STATUS_TXDV 0x00000040 54 #define CDNS_I2C_STATUS_RXOVF 0x00000080 55 #define CDNS_I2C_STATUS_BA 0x00000100 56 57 /* Interrupt register fields */ 58 #define CDNS_I2C_INTERRUPT_COMP 0x00000001 59 #define CDNS_I2C_INTERRUPT_DATA 0x00000002 60 #define CDNS_I2C_INTERRUPT_NACK 0x00000004 61 #define CDNS_I2C_INTERRUPT_TO 0x00000008 62 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 63 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 64 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 65 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 66 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 67 68 #define CDNS_I2C_FIFO_DEPTH 16 69 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ 70 71 #ifdef DEBUG 72 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) 73 { 74 int int_status; 75 int status; 76 int_status = readl(&cdns_i2c->interrupt_status); 77 78 status = readl(&cdns_i2c->status); 79 if (int_status || status) { 80 debug("Status: "); 81 if (int_status & CDNS_I2C_INTERRUPT_COMP) 82 debug("COMP "); 83 if (int_status & CDNS_I2C_INTERRUPT_DATA) 84 debug("DATA "); 85 if (int_status & CDNS_I2C_INTERRUPT_NACK) 86 debug("NACK "); 87 if (int_status & CDNS_I2C_INTERRUPT_TO) 88 debug("TO "); 89 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) 90 debug("SLVRDY "); 91 if (int_status & CDNS_I2C_INTERRUPT_RXOVF) 92 debug("RXOVF "); 93 if (int_status & CDNS_I2C_INTERRUPT_TXOVF) 94 debug("TXOVF "); 95 if (int_status & CDNS_I2C_INTERRUPT_RXUNF) 96 debug("RXUNF "); 97 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) 98 debug("ARBLOST "); 99 if (status & CDNS_I2C_STATUS_RXDV) 100 debug("RXDV "); 101 if (status & CDNS_I2C_STATUS_TXDV) 102 debug("TXDV "); 103 if (status & CDNS_I2C_STATUS_RXOVF) 104 debug("RXOVF "); 105 if (status & CDNS_I2C_STATUS_BA) 106 debug("BA "); 107 debug("TS%d ", readl(&cdns_i2c->transfer_size)); 108 debug("\n"); 109 } 110 } 111 #endif 112 113 struct i2c_cdns_bus { 114 int id; 115 struct cdns_i2c_regs __iomem *regs; /* register base */ 116 }; 117 118 119 /** cdns_i2c_probe() - Probe method 120 * @dev: udevice pointer 121 * 122 * DM callback called when device is probed 123 */ 124 static int cdns_i2c_probe(struct udevice *dev) 125 { 126 struct i2c_cdns_bus *bus = dev_get_priv(dev); 127 128 bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); 129 if (!bus->regs) 130 return -ENOMEM; 131 132 /* TODO: Calculate dividers based on CPU_CLK_1X */ 133 /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ 134 writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) | 135 (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); 136 137 /* Enable master mode, ack, and 7-bit addressing */ 138 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | 139 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); 140 141 debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); 142 143 return 0; 144 } 145 146 static int cdns_i2c_remove(struct udevice *dev) 147 { 148 struct i2c_cdns_bus *bus = dev_get_priv(dev); 149 150 debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); 151 152 unmap_sysmem(bus->regs); 153 154 return 0; 155 } 156 157 /* Wait for an interrupt */ 158 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) 159 { 160 int timeout, int_status; 161 162 for (timeout = 0; timeout < 100; timeout++) { 163 udelay(100); 164 int_status = readl(&cdns_i2c->interrupt_status); 165 if (int_status & mask) 166 break; 167 } 168 169 /* Clear interrupt status flags */ 170 writel(int_status & mask, &cdns_i2c->interrupt_status); 171 172 return int_status & mask; 173 } 174 175 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 176 { 177 if (speed != 100000) { 178 printf("%s, failed to set clock speed to %u\n", __func__, 179 speed); 180 return -EINVAL; 181 } 182 183 return 0; 184 } 185 186 /* Probe to see if a chip is present. */ 187 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, 188 uint chip_flags) 189 { 190 struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus); 191 struct cdns_i2c_regs *regs = i2c_bus->regs; 192 193 /* Attempt to read a byte */ 194 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 195 CDNS_I2C_CONTROL_RW); 196 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 197 writel(0xFF, ®s->interrupt_status); 198 writel(chip_addr, ®s->address); 199 writel(1, ®s->transfer_size); 200 201 return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 202 CDNS_I2C_INTERRUPT_NACK) & 203 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; 204 } 205 206 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 207 u32 len, bool next_is_read) 208 { 209 u8 *cur_data = data; 210 211 struct cdns_i2c_regs *regs = i2c_bus->regs; 212 213 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 214 CDNS_I2C_CONTROL_HOLD); 215 216 /* if next is a read, we need to clear HOLD, doesn't work */ 217 if (next_is_read) 218 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 219 220 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); 221 222 writel(0xFF, ®s->interrupt_status); 223 writel(addr, ®s->address); 224 225 while (len--) { 226 writel(*(cur_data++), ®s->data); 227 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { 228 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) { 229 /* Release the bus */ 230 clrbits_le32(®s->control, 231 CDNS_I2C_CONTROL_HOLD); 232 return -ETIMEDOUT; 233 } 234 } 235 } 236 237 /* All done... release the bus */ 238 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 239 /* Wait for the address and data to be sent */ 240 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) 241 return -ETIMEDOUT; 242 return 0; 243 } 244 245 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 246 u32 len) 247 { 248 u32 status; 249 u32 i = 0; 250 u8 *cur_data = data; 251 252 /* TODO: Fix this */ 253 struct cdns_i2c_regs *regs = i2c_bus->regs; 254 255 /* Check the hardware can handle the requested bytes */ 256 if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) 257 return -EINVAL; 258 259 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 260 CDNS_I2C_CONTROL_RW); 261 262 /* Start reading data */ 263 writel(addr, ®s->address); 264 writel(len, ®s->transfer_size); 265 266 /* Wait for data */ 267 do { 268 status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 269 CDNS_I2C_INTERRUPT_DATA); 270 if (!status) { 271 /* Release the bus */ 272 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 273 return -ETIMEDOUT; 274 } 275 debug("Read %d bytes\n", 276 len - readl(®s->transfer_size)); 277 for (; i < len - readl(®s->transfer_size); i++) 278 *(cur_data++) = readl(®s->data); 279 } while (readl(®s->transfer_size) != 0); 280 /* All done... release the bus */ 281 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 282 283 #ifdef DEBUG 284 cdns_i2c_debug_status(regs); 285 #endif 286 return 0; 287 } 288 289 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 290 int nmsgs) 291 { 292 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 293 int ret; 294 295 debug("i2c_xfer: %d messages\n", nmsgs); 296 for (; nmsgs > 0; nmsgs--, msg++) { 297 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 298 299 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 300 if (msg->flags & I2C_M_RD) { 301 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, 302 msg->len); 303 } else { 304 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, 305 msg->len, next_is_read); 306 } 307 if (ret) { 308 debug("i2c_write: error sending\n"); 309 return -EREMOTEIO; 310 } 311 } 312 313 return 0; 314 } 315 316 static const struct dm_i2c_ops cdns_i2c_ops = { 317 .xfer = cdns_i2c_xfer, 318 .probe_chip = cdns_i2c_probe_chip, 319 .set_bus_speed = cdns_i2c_set_bus_speed, 320 }; 321 322 static const struct udevice_id cdns_i2c_of_match[] = { 323 { .compatible = "cdns,i2c-r1p10" }, 324 { /* end of table */ } 325 }; 326 327 U_BOOT_DRIVER(cdns_i2c) = { 328 .name = "i2c-cdns", 329 .id = UCLASS_I2C, 330 .of_match = cdns_i2c_of_match, 331 .probe = cdns_i2c_probe, 332 .remove = cdns_i2c_remove, 333 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), 334 .ops = &cdns_i2c_ops, 335 }; 336