1 /* 2 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com> 3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) 4 * 5 * This file is based on: drivers/i2c/zynq_i2c.c, 6 * with added driver-model support and code cleanup. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <linux/types.h> 13 #include <linux/io.h> 14 #include <asm/errno.h> 15 #include <dm/device.h> 16 #include <dm/root.h> 17 #include <i2c.h> 18 #include <fdtdec.h> 19 #include <mapmem.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* i2c register set */ 24 struct cdns_i2c_regs { 25 u32 control; 26 u32 status; 27 u32 address; 28 u32 data; 29 u32 interrupt_status; 30 u32 transfer_size; 31 u32 slave_mon_pause; 32 u32 time_out; 33 u32 interrupt_mask; 34 u32 interrupt_enable; 35 u32 interrupt_disable; 36 }; 37 38 /* Control register fields */ 39 #define CDNS_I2C_CONTROL_RW 0x00000001 40 #define CDNS_I2C_CONTROL_MS 0x00000002 41 #define CDNS_I2C_CONTROL_NEA 0x00000004 42 #define CDNS_I2C_CONTROL_ACKEN 0x00000008 43 #define CDNS_I2C_CONTROL_HOLD 0x00000010 44 #define CDNS_I2C_CONTROL_SLVMON 0x00000020 45 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 47 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 49 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 50 51 /* Status register values */ 52 #define CDNS_I2C_STATUS_RXDV 0x00000020 53 #define CDNS_I2C_STATUS_TXDV 0x00000040 54 #define CDNS_I2C_STATUS_RXOVF 0x00000080 55 #define CDNS_I2C_STATUS_BA 0x00000100 56 57 /* Interrupt register fields */ 58 #define CDNS_I2C_INTERRUPT_COMP 0x00000001 59 #define CDNS_I2C_INTERRUPT_DATA 0x00000002 60 #define CDNS_I2C_INTERRUPT_NACK 0x00000004 61 #define CDNS_I2C_INTERRUPT_TO 0x00000008 62 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 63 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 64 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 65 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 66 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 67 68 #define CDNS_I2C_FIFO_DEPTH 16 69 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ 70 71 #ifdef DEBUG 72 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) 73 { 74 int int_status; 75 int status; 76 int_status = readl(&cdns_i2c->interrupt_status); 77 78 status = readl(&cdns_i2c->status); 79 if (int_status || status) { 80 debug("Status: "); 81 if (int_status & CDNS_I2C_INTERRUPT_COMP) 82 debug("COMP "); 83 if (int_status & CDNS_I2C_INTERRUPT_DATA) 84 debug("DATA "); 85 if (int_status & CDNS_I2C_INTERRUPT_NACK) 86 debug("NACK "); 87 if (int_status & CDNS_I2C_INTERRUPT_TO) 88 debug("TO "); 89 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) 90 debug("SLVRDY "); 91 if (int_status & CDNS_I2C_INTERRUPT_RXOVF) 92 debug("RXOVF "); 93 if (int_status & CDNS_I2C_INTERRUPT_TXOVF) 94 debug("TXOVF "); 95 if (int_status & CDNS_I2C_INTERRUPT_RXUNF) 96 debug("RXUNF "); 97 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) 98 debug("ARBLOST "); 99 if (status & CDNS_I2C_STATUS_RXDV) 100 debug("RXDV "); 101 if (status & CDNS_I2C_STATUS_TXDV) 102 debug("TXDV "); 103 if (status & CDNS_I2C_STATUS_RXOVF) 104 debug("RXOVF "); 105 if (status & CDNS_I2C_STATUS_BA) 106 debug("BA "); 107 debug("TS%d ", readl(&cdns_i2c->transfer_size)); 108 debug("\n"); 109 } 110 } 111 #endif 112 113 struct i2c_cdns_bus { 114 int id; 115 unsigned int input_freq; 116 struct cdns_i2c_regs __iomem *regs; /* register base */ 117 }; 118 119 /* Wait for an interrupt */ 120 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) 121 { 122 int timeout, int_status; 123 124 for (timeout = 0; timeout < 100; timeout++) { 125 udelay(100); 126 int_status = readl(&cdns_i2c->interrupt_status); 127 if (int_status & mask) 128 break; 129 } 130 131 /* Clear interrupt status flags */ 132 writel(int_status & mask, &cdns_i2c->interrupt_status); 133 134 return int_status & mask; 135 } 136 137 #define CDNS_I2C_DIVA_MAX 4 138 #define CDNS_I2C_DIVB_MAX 64 139 140 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 141 unsigned int *a, unsigned int *b) 142 { 143 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 144 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 145 unsigned int last_error, current_error; 146 147 /* calculate (divisor_a+1) x (divisor_b+1) */ 148 temp = input_clk / (22 * fscl); 149 150 /* 151 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX, 152 * the fscl input is out of range. Return error. 153 */ 154 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 155 return -EINVAL; 156 157 last_error = -1; 158 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 159 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 160 161 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 162 continue; 163 div_b--; 164 165 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 166 167 if (actual_fscl > fscl) 168 continue; 169 170 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 171 (fscl - actual_fscl)); 172 173 if (last_error > current_error) { 174 calc_div_a = div_a; 175 calc_div_b = div_b; 176 best_fscl = actual_fscl; 177 last_error = current_error; 178 } 179 } 180 181 *a = calc_div_a; 182 *b = calc_div_b; 183 *f = best_fscl; 184 185 return 0; 186 } 187 188 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 189 { 190 struct i2c_cdns_bus *bus = dev_get_priv(dev); 191 u32 div_a = 0, div_b = 0; 192 unsigned long speed_p = speed; 193 int ret = 0; 194 195 if (speed > 400000) { 196 debug("%s, failed to set clock speed to %u\n", __func__, 197 speed); 198 return -EINVAL; 199 } 200 201 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b); 202 if (ret) 203 return ret; 204 205 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n", 206 __func__, div_a, div_b, bus->input_freq, speed, speed_p); 207 208 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) | 209 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); 210 211 /* Enable master mode, ack, and 7-bit addressing */ 212 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | 213 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); 214 215 return 0; 216 } 217 218 /* Probe to see if a chip is present. */ 219 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, 220 uint chip_flags) 221 { 222 struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus); 223 struct cdns_i2c_regs *regs = i2c_bus->regs; 224 225 /* Attempt to read a byte */ 226 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 227 CDNS_I2C_CONTROL_RW); 228 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 229 writel(0xFF, ®s->interrupt_status); 230 writel(chip_addr, ®s->address); 231 writel(1, ®s->transfer_size); 232 233 return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 234 CDNS_I2C_INTERRUPT_NACK) & 235 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; 236 } 237 238 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 239 u32 len, bool next_is_read) 240 { 241 u8 *cur_data = data; 242 243 struct cdns_i2c_regs *regs = i2c_bus->regs; 244 245 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 246 CDNS_I2C_CONTROL_HOLD); 247 248 /* if next is a read, we need to clear HOLD, doesn't work */ 249 if (next_is_read) 250 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 251 252 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); 253 254 writel(0xFF, ®s->interrupt_status); 255 writel(addr, ®s->address); 256 257 while (len--) { 258 writel(*(cur_data++), ®s->data); 259 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { 260 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) { 261 /* Release the bus */ 262 clrbits_le32(®s->control, 263 CDNS_I2C_CONTROL_HOLD); 264 return -ETIMEDOUT; 265 } 266 } 267 } 268 269 /* All done... release the bus */ 270 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 271 /* Wait for the address and data to be sent */ 272 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) 273 return -ETIMEDOUT; 274 return 0; 275 } 276 277 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 278 u32 len) 279 { 280 u32 status; 281 u32 i = 0; 282 u8 *cur_data = data; 283 284 /* TODO: Fix this */ 285 struct cdns_i2c_regs *regs = i2c_bus->regs; 286 287 /* Check the hardware can handle the requested bytes */ 288 if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) 289 return -EINVAL; 290 291 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 292 CDNS_I2C_CONTROL_RW); 293 294 /* Start reading data */ 295 writel(addr, ®s->address); 296 writel(len, ®s->transfer_size); 297 298 /* Wait for data */ 299 do { 300 status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 301 CDNS_I2C_INTERRUPT_DATA); 302 if (!status) { 303 /* Release the bus */ 304 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 305 return -ETIMEDOUT; 306 } 307 debug("Read %d bytes\n", 308 len - readl(®s->transfer_size)); 309 for (; i < len - readl(®s->transfer_size); i++) 310 *(cur_data++) = readl(®s->data); 311 } while (readl(®s->transfer_size) != 0); 312 /* All done... release the bus */ 313 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 314 315 #ifdef DEBUG 316 cdns_i2c_debug_status(regs); 317 #endif 318 return 0; 319 } 320 321 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 322 int nmsgs) 323 { 324 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 325 int ret; 326 327 debug("i2c_xfer: %d messages\n", nmsgs); 328 for (; nmsgs > 0; nmsgs--, msg++) { 329 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 330 331 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 332 if (msg->flags & I2C_M_RD) { 333 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, 334 msg->len); 335 } else { 336 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, 337 msg->len, next_is_read); 338 } 339 if (ret) { 340 debug("i2c_write: error sending\n"); 341 return -EREMOTEIO; 342 } 343 } 344 345 return 0; 346 } 347 348 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) 349 { 350 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 351 352 i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); 353 if (!i2c_bus->regs) 354 return -ENOMEM; 355 356 i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */ 357 358 return 0; 359 } 360 361 static const struct dm_i2c_ops cdns_i2c_ops = { 362 .xfer = cdns_i2c_xfer, 363 .probe_chip = cdns_i2c_probe_chip, 364 .set_bus_speed = cdns_i2c_set_bus_speed, 365 }; 366 367 static const struct udevice_id cdns_i2c_of_match[] = { 368 { .compatible = "cdns,i2c-r1p10" }, 369 { /* end of table */ } 370 }; 371 372 U_BOOT_DRIVER(cdns_i2c) = { 373 .name = "i2c-cdns", 374 .id = UCLASS_I2C, 375 .of_match = cdns_i2c_of_match, 376 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata, 377 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), 378 .ops = &cdns_i2c_ops, 379 }; 380