1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com> 4 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) 5 * 6 * This file is based on: drivers/i2c/zynq_i2c.c, 7 * with added driver-model support and code cleanup. 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <linux/types.h> 13 #include <linux/io.h> 14 #include <linux/errno.h> 15 #include <dm/root.h> 16 #include <i2c.h> 17 #include <fdtdec.h> 18 #include <mapmem.h> 19 #include <wait_bit.h> 20 #include <clk.h> 21 22 /* i2c register set */ 23 struct cdns_i2c_regs { 24 u32 control; 25 u32 status; 26 u32 address; 27 u32 data; 28 u32 interrupt_status; 29 u32 transfer_size; 30 u32 slave_mon_pause; 31 u32 time_out; 32 u32 interrupt_mask; 33 u32 interrupt_enable; 34 u32 interrupt_disable; 35 }; 36 37 /* Control register fields */ 38 #define CDNS_I2C_CONTROL_RW 0x00000001 39 #define CDNS_I2C_CONTROL_MS 0x00000002 40 #define CDNS_I2C_CONTROL_NEA 0x00000004 41 #define CDNS_I2C_CONTROL_ACKEN 0x00000008 42 #define CDNS_I2C_CONTROL_HOLD 0x00000010 43 #define CDNS_I2C_CONTROL_SLVMON 0x00000020 44 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 45 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 46 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 47 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 48 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 49 50 /* Status register values */ 51 #define CDNS_I2C_STATUS_RXDV 0x00000020 52 #define CDNS_I2C_STATUS_TXDV 0x00000040 53 #define CDNS_I2C_STATUS_RXOVF 0x00000080 54 #define CDNS_I2C_STATUS_BA 0x00000100 55 56 /* Interrupt register fields */ 57 #define CDNS_I2C_INTERRUPT_COMP 0x00000001 58 #define CDNS_I2C_INTERRUPT_DATA 0x00000002 59 #define CDNS_I2C_INTERRUPT_NACK 0x00000004 60 #define CDNS_I2C_INTERRUPT_TO 0x00000008 61 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 62 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 63 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 64 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 65 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 66 67 #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \ 68 CDNS_I2C_INTERRUPT_DATA | \ 69 CDNS_I2C_INTERRUPT_NACK | \ 70 CDNS_I2C_INTERRUPT_TO | \ 71 CDNS_I2C_INTERRUPT_SLVRDY | \ 72 CDNS_I2C_INTERRUPT_RXOVF | \ 73 CDNS_I2C_INTERRUPT_TXOVF | \ 74 CDNS_I2C_INTERRUPT_RXUNF | \ 75 CDNS_I2C_INTERRUPT_ARBLOST) 76 77 #define CDNS_I2C_FIFO_DEPTH 16 78 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ 79 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3) 80 81 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 82 83 #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10 84 85 #ifdef DEBUG 86 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) 87 { 88 int int_status; 89 int status; 90 int_status = readl(&cdns_i2c->interrupt_status); 91 92 status = readl(&cdns_i2c->status); 93 if (int_status || status) { 94 debug("Status: "); 95 if (int_status & CDNS_I2C_INTERRUPT_COMP) 96 debug("COMP "); 97 if (int_status & CDNS_I2C_INTERRUPT_DATA) 98 debug("DATA "); 99 if (int_status & CDNS_I2C_INTERRUPT_NACK) 100 debug("NACK "); 101 if (int_status & CDNS_I2C_INTERRUPT_TO) 102 debug("TO "); 103 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) 104 debug("SLVRDY "); 105 if (int_status & CDNS_I2C_INTERRUPT_RXOVF) 106 debug("RXOVF "); 107 if (int_status & CDNS_I2C_INTERRUPT_TXOVF) 108 debug("TXOVF "); 109 if (int_status & CDNS_I2C_INTERRUPT_RXUNF) 110 debug("RXUNF "); 111 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) 112 debug("ARBLOST "); 113 if (status & CDNS_I2C_STATUS_RXDV) 114 debug("RXDV "); 115 if (status & CDNS_I2C_STATUS_TXDV) 116 debug("TXDV "); 117 if (status & CDNS_I2C_STATUS_RXOVF) 118 debug("RXOVF "); 119 if (status & CDNS_I2C_STATUS_BA) 120 debug("BA "); 121 debug("TS%d ", readl(&cdns_i2c->transfer_size)); 122 debug("\n"); 123 } 124 } 125 #endif 126 127 struct i2c_cdns_bus { 128 int id; 129 unsigned int input_freq; 130 struct cdns_i2c_regs __iomem *regs; /* register base */ 131 132 int hold_flag; 133 u32 quirks; 134 }; 135 136 struct cdns_i2c_platform_data { 137 u32 quirks; 138 }; 139 140 /* Wait for an interrupt */ 141 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) 142 { 143 int timeout, int_status; 144 145 for (timeout = 0; timeout < 100; timeout++) { 146 int_status = readl(&cdns_i2c->interrupt_status); 147 if (int_status & mask) 148 break; 149 udelay(100); 150 } 151 152 /* Clear interrupt status flags */ 153 writel(int_status & mask, &cdns_i2c->interrupt_status); 154 155 return int_status & mask; 156 } 157 158 #define CDNS_I2C_DIVA_MAX 4 159 #define CDNS_I2C_DIVB_MAX 64 160 161 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 162 unsigned int *a, unsigned int *b) 163 { 164 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 165 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 166 unsigned int last_error, current_error; 167 168 /* calculate (divisor_a+1) x (divisor_b+1) */ 169 temp = input_clk / (22 * fscl); 170 171 /* 172 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX, 173 * the fscl input is out of range. Return error. 174 */ 175 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 176 return -EINVAL; 177 178 last_error = -1; 179 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 180 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 181 182 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 183 continue; 184 div_b--; 185 186 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 187 188 if (actual_fscl > fscl) 189 continue; 190 191 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 192 (fscl - actual_fscl)); 193 194 if (last_error > current_error) { 195 calc_div_a = div_a; 196 calc_div_b = div_b; 197 best_fscl = actual_fscl; 198 last_error = current_error; 199 } 200 } 201 202 *a = calc_div_a; 203 *b = calc_div_b; 204 *f = best_fscl; 205 206 return 0; 207 } 208 209 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 210 { 211 struct i2c_cdns_bus *bus = dev_get_priv(dev); 212 u32 div_a = 0, div_b = 0; 213 unsigned long speed_p = speed; 214 int ret = 0; 215 216 if (speed > 400000) { 217 debug("%s, failed to set clock speed to %u\n", __func__, 218 speed); 219 return -EINVAL; 220 } 221 222 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b); 223 if (ret) 224 return ret; 225 226 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n", 227 __func__, div_a, div_b, bus->input_freq, speed, speed_p); 228 229 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) | 230 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); 231 232 /* Enable master mode, ack, and 7-bit addressing */ 233 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | 234 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); 235 236 return 0; 237 } 238 239 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs) 240 { 241 return (readl(®s->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST); 242 } 243 244 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 245 u32 len) 246 { 247 u8 *cur_data = data; 248 struct cdns_i2c_regs *regs = i2c_bus->regs; 249 u32 ret; 250 251 /* Set the controller in Master transmit mode and clear FIFO */ 252 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO); 253 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); 254 255 /* Check message size against FIFO depth, and set hold bus bit 256 * if it is greater than FIFO depth 257 */ 258 if (len > CDNS_I2C_FIFO_DEPTH) 259 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 260 261 /* Clear the interrupts in status register */ 262 writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status); 263 264 writel(addr, ®s->address); 265 266 while (len-- && !is_arbitration_lost(regs)) { 267 writel(*(cur_data++), ®s->data); 268 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { 269 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 270 CDNS_I2C_INTERRUPT_ARBLOST); 271 if (ret & CDNS_I2C_INTERRUPT_ARBLOST) 272 return -EAGAIN; 273 if (ret & CDNS_I2C_INTERRUPT_COMP) 274 continue; 275 /* Release the bus */ 276 clrbits_le32(®s->control, 277 CDNS_I2C_CONTROL_HOLD); 278 return -ETIMEDOUT; 279 } 280 } 281 282 if (len && is_arbitration_lost(regs)) 283 return -EAGAIN; 284 285 /* All done... release the bus */ 286 if (!i2c_bus->hold_flag) 287 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 288 289 /* Wait for the address and data to be sent */ 290 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 291 CDNS_I2C_INTERRUPT_ARBLOST); 292 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST | 293 CDNS_I2C_INTERRUPT_COMP))) 294 return -ETIMEDOUT; 295 if (ret & CDNS_I2C_INTERRUPT_ARBLOST) 296 return -EAGAIN; 297 298 return 0; 299 } 300 301 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count) 302 { 303 return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1); 304 } 305 306 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 307 u32 recv_count) 308 { 309 u8 *cur_data = data; 310 struct cdns_i2c_regs *regs = i2c_bus->regs; 311 int curr_recv_count; 312 int updatetx, hold_quirk; 313 u32 ret; 314 315 /* Check the hardware can handle the requested bytes */ 316 if ((recv_count < 0)) 317 return -EINVAL; 318 319 curr_recv_count = recv_count; 320 321 /* Check for the message size against the FIFO depth */ 322 if (recv_count > CDNS_I2C_FIFO_DEPTH) 323 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 324 325 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 326 CDNS_I2C_CONTROL_RW); 327 328 if (recv_count > CDNS_I2C_TRANSFER_SIZE) { 329 curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 330 writel(curr_recv_count, ®s->transfer_size); 331 } else { 332 writel(recv_count, ®s->transfer_size); 333 } 334 335 /* Start reading data */ 336 writel(addr, ®s->address); 337 338 updatetx = recv_count > curr_recv_count; 339 340 hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx; 341 342 while (recv_count && !is_arbitration_lost(regs)) { 343 while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) { 344 if (recv_count < CDNS_I2C_FIFO_DEPTH && 345 !i2c_bus->hold_flag) { 346 clrbits_le32(®s->control, 347 CDNS_I2C_CONTROL_HOLD); 348 } 349 *(cur_data)++ = readl(®s->data); 350 recv_count--; 351 curr_recv_count--; 352 353 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) 354 break; 355 } 356 357 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) { 358 /* wait while fifo is full */ 359 while (readl(®s->transfer_size) != 360 (curr_recv_count - CDNS_I2C_FIFO_DEPTH)) 361 ; 362 /* 363 * Check number of bytes to be received against maximum 364 * transfer size and update register accordingly. 365 */ 366 if ((recv_count - CDNS_I2C_FIFO_DEPTH) > 367 CDNS_I2C_TRANSFER_SIZE) { 368 writel(CDNS_I2C_TRANSFER_SIZE, 369 ®s->transfer_size); 370 curr_recv_count = CDNS_I2C_TRANSFER_SIZE + 371 CDNS_I2C_FIFO_DEPTH; 372 } else { 373 writel(recv_count - CDNS_I2C_FIFO_DEPTH, 374 ®s->transfer_size); 375 curr_recv_count = recv_count; 376 } 377 } else if (recv_count && !hold_quirk && !curr_recv_count) { 378 writel(addr, ®s->address); 379 if (recv_count > CDNS_I2C_TRANSFER_SIZE) { 380 writel(CDNS_I2C_TRANSFER_SIZE, 381 ®s->transfer_size); 382 curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 383 } else { 384 writel(recv_count, ®s->transfer_size); 385 curr_recv_count = recv_count; 386 } 387 } 388 } 389 390 /* Wait for the address and data to be sent */ 391 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 392 CDNS_I2C_INTERRUPT_ARBLOST); 393 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST | 394 CDNS_I2C_INTERRUPT_COMP))) 395 return -ETIMEDOUT; 396 if (ret & CDNS_I2C_INTERRUPT_ARBLOST) 397 return -EAGAIN; 398 399 return 0; 400 } 401 402 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 403 int nmsgs) 404 { 405 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 406 int ret = 0; 407 int count; 408 bool hold_quirk; 409 struct i2c_msg *message = msg; 410 int num_msgs = nmsgs; 411 412 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 413 414 if (nmsgs > 1) { 415 /* 416 * This controller does not give completion interrupt after a 417 * master receive message if HOLD bit is set (repeated start), 418 * resulting in SW timeout. Hence, if a receive message is 419 * followed by any other message, an error is returned 420 * indicating that this sequence is not supported. 421 */ 422 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) { 423 if (msg[count].flags & I2C_M_RD) { 424 printf("Can't do repeated start after a receive message\n"); 425 return -EOPNOTSUPP; 426 } 427 } 428 429 i2c_bus->hold_flag = 1; 430 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD); 431 } else { 432 i2c_bus->hold_flag = 0; 433 } 434 435 debug("i2c_xfer: %d messages\n", nmsgs); 436 for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES && 437 nmsgs > 0; nmsgs--, msg++) { 438 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 439 if (msg->flags & I2C_M_RD) { 440 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, 441 msg->len); 442 } else { 443 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, 444 msg->len); 445 } 446 if (ret == -EAGAIN) { 447 msg = message; 448 nmsgs = num_msgs; 449 retry++; 450 printf("%s,arbitration lost, retrying:%d\n", __func__, 451 retry); 452 continue; 453 } 454 455 if (ret) { 456 debug("i2c_write: error sending\n"); 457 return -EREMOTEIO; 458 } 459 } 460 461 return ret; 462 } 463 464 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) 465 { 466 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 467 struct cdns_i2c_platform_data *pdata = 468 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev); 469 struct clk clk; 470 int ret; 471 472 i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev); 473 if (!i2c_bus->regs) 474 return -ENOMEM; 475 476 if (pdata) 477 i2c_bus->quirks = pdata->quirks; 478 479 ret = clk_get_by_index(dev, 0, &clk); 480 if (ret) 481 return ret; 482 483 i2c_bus->input_freq = clk_get_rate(&clk); 484 485 return 0; 486 } 487 488 static const struct dm_i2c_ops cdns_i2c_ops = { 489 .xfer = cdns_i2c_xfer, 490 .set_bus_speed = cdns_i2c_set_bus_speed, 491 }; 492 493 static const struct cdns_i2c_platform_data r1p10_i2c_def = { 494 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 495 }; 496 497 static const struct udevice_id cdns_i2c_of_match[] = { 498 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def }, 499 { .compatible = "cdns,i2c-r1p14" }, 500 { /* end of table */ } 501 }; 502 503 U_BOOT_DRIVER(cdns_i2c) = { 504 .name = "i2c-cdns", 505 .id = UCLASS_I2C, 506 .of_match = cdns_i2c_of_match, 507 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata, 508 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), 509 .ops = &cdns_i2c_ops, 510 }; 511