1 /* 2 * Copyright 2006,2009 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 /* The maximum number of microseconds we will wait until another master has 30 * released the bus. If not defined in the board header file, then use a 31 * generic value. 32 */ 33 #ifndef CONFIG_I2C_MBB_TIMEOUT 34 #define CONFIG_I2C_MBB_TIMEOUT 100000 35 #endif 36 37 /* The maximum number of microseconds we will wait for a read or write 38 * operation to complete. If not defined in the board header file, then use a 39 * generic value. 40 */ 41 #ifndef CONFIG_I2C_TIMEOUT 42 #define CONFIG_I2C_TIMEOUT 10000 43 #endif 44 45 #define I2C_READ_BIT 1 46 #define I2C_WRITE_BIT 0 47 48 DECLARE_GLOBAL_DATA_PTR; 49 50 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 51 * Default is bus 0. This is necessary because the DDR initialization 52 * runs from ROM, and we can't switch buses because we can't modify 53 * the global variables. 54 */ 55 #ifndef CONFIG_SYS_SPD_BUS_NUM 56 #define CONFIG_SYS_SPD_BUS_NUM 0 57 #endif 58 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; 59 #if defined(CONFIG_I2C_MUX) 60 static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; 61 #endif 62 63 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; 64 65 static const struct fsl_i2c *i2c_dev[2] = { 66 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), 67 #ifdef CONFIG_SYS_I2C2_OFFSET 68 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) 69 #endif 70 }; 71 72 /* I2C speed map for a DFSR value of 1 */ 73 74 /* 75 * Map I2C frequency dividers to FDR and DFSR values 76 * 77 * This structure is used to define the elements of a table that maps I2C 78 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 79 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 80 * Sampling Rate (DFSR) registers. 81 * 82 * The actual table should be defined in the board file, and it must be called 83 * fsl_i2c_speed_map[]. 84 * 85 * The last entry of the table must have a value of {-1, X}, where X is same 86 * FDR/DFSR values as the second-to-last entry. This guarantees that any 87 * search through the array will always find a match. 88 * 89 * The values of the divider must be in increasing numerical order, i.e. 90 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 91 * 92 * For this table, the values are based on a value of 1 for the DFSR 93 * register. See the application note AN2919 "Determining the I2C Frequency 94 * Divider Ratio for SCL" 95 * 96 * ColdFire I2C frequency dividers for FDR values are different from 97 * PowerPC. The protocol to use the I2C module is still the same. 98 * A different table is defined and are based on MCF5xxx user manual. 99 * 100 */ 101 static const struct { 102 unsigned short divider; 103 u8 fdr; 104 } fsl_i2c_speed_map[] = { 105 #ifdef __M68K__ 106 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 107 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 108 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 109 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 110 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 111 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 112 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 113 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 114 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 115 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 116 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 117 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 118 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 119 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 120 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 121 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 122 {-1, 31} 123 #endif 124 }; 125 126 /** 127 * Set the I2C bus speed for a given I2C device 128 * 129 * @param dev: the I2C device 130 * @i2c_clk: I2C bus clock frequency 131 * @speed: the desired speed of the bus 132 * 133 * The I2C device must be stopped before calling this function. 134 * 135 * The return value is the actual bus speed that is set. 136 */ 137 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 138 unsigned int i2c_clk, unsigned int speed) 139 { 140 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 141 142 /* 143 * We want to choose an FDR/DFSR that generates an I2C bus speed that 144 * is equal to or lower than the requested speed. That means that we 145 * want the first divider that is equal to or greater than the 146 * calculated divider. 147 */ 148 #ifdef __PPC__ 149 u8 dfsr, fdr = 0x31; /* Default if no FDR found */ 150 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ 151 unsigned short a, b, ga, gb; 152 unsigned long c_div, est_div; 153 154 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR 155 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; 156 #else 157 /* Condition 1: dfsr <= 50/T */ 158 dfsr = (5 * (i2c_clk / 1000)) / 100000; 159 #endif 160 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR 161 fdr = CONFIG_FSL_I2C_CUSTOM_FDR; 162 speed = i2c_clk / divider; /* Fake something */ 163 #else 164 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk); 165 if (!dfsr) 166 dfsr = 1; 167 168 est_div = ~0; 169 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { 170 for (gb = 0; gb < 8; gb++) { 171 b = 16 << gb; 172 c_div = b * (a + ((3*dfsr)/b)*2); 173 if ((c_div > divider) && (c_div < est_div)) { 174 unsigned short bin_gb, bin_ga; 175 176 est_div = c_div; 177 bin_gb = gb << 2; 178 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); 179 fdr = bin_gb | bin_ga; 180 speed = i2c_clk / est_div; 181 debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, " 182 "a:%d, b:%d, speed:%d\n", 183 fdr, est_div, ga, gb, a, b, speed); 184 /* Condition 2 not accounted for */ 185 debug("Tr <= %d ns\n", 186 (b - 3 * dfsr) * 1000000 / 187 (i2c_clk / 1000)); 188 } 189 } 190 if (a == 20) 191 a += 2; 192 if (a == 24) 193 a += 4; 194 } 195 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); 196 debug("FDR:0x%.2x, speed:%d\n", fdr, speed); 197 #endif 198 writeb(dfsr, &dev->dfsrr); /* set default filter */ 199 writeb(fdr, &dev->fdr); /* set bus speed */ 200 #else 201 unsigned int i; 202 203 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 204 if (fsl_i2c_speed_map[i].divider >= divider) { 205 u8 fdr; 206 207 fdr = fsl_i2c_speed_map[i].fdr; 208 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 209 writeb(fdr, &dev->fdr); /* set bus speed */ 210 211 break; 212 } 213 #endif 214 return speed; 215 } 216 217 void 218 i2c_init(int speed, int slaveadd) 219 { 220 struct fsl_i2c *dev; 221 unsigned int temp; 222 223 #ifdef CONFIG_SYS_I2C_INIT_BOARD 224 /* Call board specific i2c bus reset routine before accessing the 225 * environment, which might be in a chip on that bus. For details 226 * about this problem see doc/I2C_Edge_Conditions. 227 */ 228 i2c_init_board(); 229 #endif 230 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); 231 232 writeb(0, &dev->cr); /* stop I2C controller */ 233 udelay(5); /* let it shutdown in peace */ 234 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 235 if (gd->flags & GD_FLG_RELOC) 236 i2c_bus_speed[0] = temp; 237 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 238 writeb(0x0, &dev->sr); /* clear status register */ 239 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 240 241 #ifdef CONFIG_SYS_I2C2_OFFSET 242 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); 243 244 writeb(0, &dev->cr); /* stop I2C controller */ 245 udelay(5); /* let it shutdown in peace */ 246 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 247 if (gd->flags & GD_FLG_RELOC) 248 i2c_bus_speed[1] = temp; 249 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 250 writeb(0x0, &dev->sr); /* clear status register */ 251 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 252 #endif 253 254 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT 255 /* Call board specific i2c bus reset routine AFTER the bus has been 256 * initialized. Use either this callpoint or i2c_init_board; 257 * which is called before i2c_init operations. 258 * For details about this problem see doc/I2C_Edge_Conditions. 259 */ 260 i2c_board_late_init(); 261 #endif 262 } 263 264 static int 265 i2c_wait4bus(void) 266 { 267 unsigned long long timeval = get_ticks(); 268 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); 269 270 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 271 if ((get_ticks() - timeval) > timeout) 272 return -1; 273 } 274 275 return 0; 276 } 277 278 static __inline__ int 279 i2c_wait(int write) 280 { 281 u32 csr; 282 unsigned long long timeval = get_ticks(); 283 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); 284 285 do { 286 csr = readb(&i2c_dev[i2c_bus_num]->sr); 287 if (!(csr & I2C_SR_MIF)) 288 continue; 289 /* Read again to allow register to stabilise */ 290 csr = readb(&i2c_dev[i2c_bus_num]->sr); 291 292 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 293 294 if (csr & I2C_SR_MAL) { 295 debug("i2c_wait: MAL\n"); 296 return -1; 297 } 298 299 if (!(csr & I2C_SR_MCF)) { 300 debug("i2c_wait: unfinished\n"); 301 return -1; 302 } 303 304 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 305 debug("i2c_wait: No RXACK\n"); 306 return -1; 307 } 308 309 return 0; 310 } while ((get_ticks() - timeval) < timeout); 311 312 debug("i2c_wait: timed out\n"); 313 return -1; 314 } 315 316 static __inline__ int 317 i2c_write_addr (u8 dev, u8 dir, int rsta) 318 { 319 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 320 | (rsta ? I2C_CR_RSTA : 0), 321 &i2c_dev[i2c_bus_num]->cr); 322 323 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 324 325 if (i2c_wait(I2C_WRITE_BIT) < 0) 326 return 0; 327 328 return 1; 329 } 330 331 static __inline__ int 332 __i2c_write(u8 *data, int length) 333 { 334 int i; 335 336 for (i = 0; i < length; i++) { 337 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 338 339 if (i2c_wait(I2C_WRITE_BIT) < 0) 340 break; 341 } 342 343 return i; 344 } 345 346 static __inline__ int 347 __i2c_read(u8 *data, int length) 348 { 349 int i; 350 351 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 352 &i2c_dev[i2c_bus_num]->cr); 353 354 /* dummy read */ 355 readb(&i2c_dev[i2c_bus_num]->dr); 356 357 for (i = 0; i < length; i++) { 358 if (i2c_wait(I2C_READ_BIT) < 0) 359 break; 360 361 /* Generate ack on last next to last byte */ 362 if (i == length - 2) 363 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 364 &i2c_dev[i2c_bus_num]->cr); 365 366 /* Do not generate stop on last byte */ 367 if (i == length - 1) 368 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 369 &i2c_dev[i2c_bus_num]->cr); 370 371 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 372 } 373 374 return i; 375 } 376 377 int 378 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 379 { 380 int i = -1; /* signal error */ 381 u8 *a = (u8*)&addr; 382 383 if (i2c_wait4bus() >= 0 384 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 385 && __i2c_write(&a[4 - alen], alen) == alen) 386 i = 0; /* No error so far */ 387 388 if (length 389 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 390 i = __i2c_read(data, length); 391 392 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 393 394 if (i2c_wait4bus()) /* Wait until STOP */ 395 debug("i2c_read: wait4bus timed out\n"); 396 397 if (i == length) 398 return 0; 399 400 return -1; 401 } 402 403 int 404 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 405 { 406 int i = -1; /* signal error */ 407 u8 *a = (u8*)&addr; 408 409 if (i2c_wait4bus() >= 0 410 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 411 && __i2c_write(&a[4 - alen], alen) == alen) { 412 i = __i2c_write(data, length); 413 } 414 415 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 416 if (i2c_wait4bus()) /* Wait until STOP */ 417 debug("i2c_write: wait4bus timed out\n"); 418 419 if (i == length) 420 return 0; 421 422 return -1; 423 } 424 425 int 426 i2c_probe(uchar chip) 427 { 428 /* For unknow reason the controller will ACK when 429 * probing for a slave with the same address, so skip 430 * it. 431 */ 432 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 433 return -1; 434 435 return i2c_read(chip, 0, 0, NULL, 0); 436 } 437 438 int i2c_set_bus_num(unsigned int bus) 439 { 440 #if defined(CONFIG_I2C_MUX) 441 if (bus < CONFIG_SYS_MAX_I2C_BUS) { 442 i2c_bus_num = bus; 443 } else { 444 int ret; 445 446 ret = i2x_mux_select_mux(bus); 447 if (ret) 448 return ret; 449 i2c_bus_num = 0; 450 } 451 i2c_bus_num_mux = bus; 452 #else 453 #ifdef CONFIG_SYS_I2C2_OFFSET 454 if (bus > 1) { 455 #else 456 if (bus > 0) { 457 #endif 458 return -1; 459 } 460 461 i2c_bus_num = bus; 462 #endif 463 return 0; 464 } 465 466 int i2c_set_bus_speed(unsigned int speed) 467 { 468 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 469 470 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 471 i2c_bus_speed[i2c_bus_num] = 472 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 473 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 474 475 return 0; 476 } 477 478 unsigned int i2c_get_bus_num(void) 479 { 480 #if defined(CONFIG_I2C_MUX) 481 return i2c_bus_num_mux; 482 #else 483 return i2c_bus_num; 484 #endif 485 } 486 487 unsigned int i2c_get_bus_speed(void) 488 { 489 return i2c_bus_speed[i2c_bus_num]; 490 } 491 492 #endif /* CONFIG_HARD_I2C */ 493