1 /* 2 * Copyright 2006 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_FSL_I2C 22 #ifdef CONFIG_HARD_I2C 23 24 #include <command.h> 25 #include <i2c.h> /* Functional interface */ 26 27 #include <asm/io.h> 28 #include <asm/fsl_i2c.h> /* HW definitions */ 29 30 #define I2C_TIMEOUT (CFG_HZ / 4) 31 32 #define I2C_READ_BIT 1 33 #define I2C_WRITE_BIT 0 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 38 * Default is bus 0. This is necessary because the DDR initialization 39 * runs from ROM, and we can't switch buses because we can't modify 40 * the global variables. 41 */ 42 #ifdef CFG_SPD_BUS_NUM 43 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; 44 #else 45 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; 46 #endif 47 48 static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED}; 49 50 static const struct fsl_i2c *i2c_dev[2] = { 51 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), 52 #ifdef CFG_I2C2_OFFSET 53 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) 54 #endif 55 }; 56 57 /* I2C speed map for a DFSR value of 1 */ 58 59 /* 60 * Map I2C frequency dividers to FDR and DFSR values 61 * 62 * This structure is used to define the elements of a table that maps I2C 63 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 64 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 65 * Sampling Rate (DFSR) registers. 66 * 67 * The actual table should be defined in the board file, and it must be called 68 * fsl_i2c_speed_map[]. 69 * 70 * The last entry of the table must have a value of {-1, X}, where X is same 71 * FDR/DFSR values as the second-to-last entry. This guarantees that any 72 * search through the array will always find a match. 73 * 74 * The values of the divider must be in increasing numerical order, i.e. 75 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 76 * 77 * For this table, the values are based on a value of 1 for the DFSR 78 * register. See the application note AN2919 "Determining the I2C Frequency 79 * Divider Ratio for SCL" 80 */ 81 static const struct { 82 unsigned short divider; 83 u8 dfsr; 84 u8 fdr; 85 } fsl_i2c_speed_map[] = { 86 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, 87 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, 88 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, 89 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, 90 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, 91 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, 92 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, 93 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, 94 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, 95 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, 96 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, 97 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, 98 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, 99 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, 100 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, 101 {61440, 1, 31}, {-1, 1, 31} 102 }; 103 104 /** 105 * Set the I2C bus speed for a given I2C device 106 * 107 * @param dev: the I2C device 108 * @i2c_clk: I2C bus clock frequency 109 * @speed: the desired speed of the bus 110 * 111 * The I2C device must be stopped before calling this function. 112 * 113 * The return value is the actual bus speed that is set. 114 */ 115 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 116 unsigned int i2c_clk, unsigned int speed) 117 { 118 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 119 unsigned int i; 120 u8 fdr, dfsr; 121 122 /* 123 * We want to choose an FDR/DFSR that generates an I2C bus speed that 124 * is equal to or lower than the requested speed. That means that we 125 * want the first divider that is equal to or greater than the 126 * calculated divider. 127 */ 128 129 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 130 if (fsl_i2c_speed_map[i].divider >= divider) { 131 dfsr = fsl_i2c_speed_map[i].dfsr; 132 fdr = fsl_i2c_speed_map[i].fdr; 133 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 134 break; 135 } 136 137 writeb(fdr, &dev->fdr); /* set bus speed */ 138 writeb(dfsr, &dev->dfsrr); /* set default filter */ 139 140 return speed; 141 } 142 143 void 144 i2c_init(int speed, int slaveadd) 145 { 146 struct fsl_i2c *dev; 147 148 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); 149 150 writeb(0, &dev->cr); /* stop I2C controller */ 151 udelay(5); /* let it shutdown in peace */ 152 i2c_bus_speed[0] = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 153 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 154 writeb(0x0, &dev->sr); /* clear status register */ 155 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 156 157 #ifdef CFG_I2C2_OFFSET 158 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); 159 160 writeb(0, &dev->cr); /* stop I2C controller */ 161 udelay(5); /* let it shutdown in peace */ 162 i2c_bus_speed[1] = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 163 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 164 writeb(0x0, &dev->sr); /* clear status register */ 165 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 166 #endif 167 } 168 169 static __inline__ int 170 i2c_wait4bus(void) 171 { 172 ulong timeval = get_timer(0); 173 174 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 175 if (get_timer(timeval) > I2C_TIMEOUT) { 176 return -1; 177 } 178 } 179 180 return 0; 181 } 182 183 static __inline__ int 184 i2c_wait(int write) 185 { 186 u32 csr; 187 ulong timeval = get_timer(0); 188 189 do { 190 csr = readb(&i2c_dev[i2c_bus_num]->sr); 191 if (!(csr & I2C_SR_MIF)) 192 continue; 193 194 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 195 196 if (csr & I2C_SR_MAL) { 197 debug("i2c_wait: MAL\n"); 198 return -1; 199 } 200 201 if (!(csr & I2C_SR_MCF)) { 202 debug("i2c_wait: unfinished\n"); 203 return -1; 204 } 205 206 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 207 debug("i2c_wait: No RXACK\n"); 208 return -1; 209 } 210 211 return 0; 212 } while (get_timer (timeval) < I2C_TIMEOUT); 213 214 debug("i2c_wait: timed out\n"); 215 return -1; 216 } 217 218 static __inline__ int 219 i2c_write_addr (u8 dev, u8 dir, int rsta) 220 { 221 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 222 | (rsta ? I2C_CR_RSTA : 0), 223 &i2c_dev[i2c_bus_num]->cr); 224 225 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 226 227 if (i2c_wait(I2C_WRITE_BIT) < 0) 228 return 0; 229 230 return 1; 231 } 232 233 static __inline__ int 234 __i2c_write(u8 *data, int length) 235 { 236 int i; 237 238 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 239 &i2c_dev[i2c_bus_num]->cr); 240 241 for (i = 0; i < length; i++) { 242 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 243 244 if (i2c_wait(I2C_WRITE_BIT) < 0) 245 break; 246 } 247 248 return i; 249 } 250 251 static __inline__ int 252 __i2c_read(u8 *data, int length) 253 { 254 int i; 255 256 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 257 &i2c_dev[i2c_bus_num]->cr); 258 259 /* dummy read */ 260 readb(&i2c_dev[i2c_bus_num]->dr); 261 262 for (i = 0; i < length; i++) { 263 if (i2c_wait(I2C_READ_BIT) < 0) 264 break; 265 266 /* Generate ack on last next to last byte */ 267 if (i == length - 2) 268 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 269 &i2c_dev[i2c_bus_num]->cr); 270 271 /* Generate stop on last byte */ 272 if (i == length - 1) 273 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); 274 275 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 276 } 277 278 return i; 279 } 280 281 int 282 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 283 { 284 int i = -1; /* signal error */ 285 u8 *a = (u8*)&addr; 286 287 if (i2c_wait4bus() >= 0 288 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 289 && __i2c_write(&a[4 - alen], alen) == alen) 290 i = 0; /* No error so far */ 291 292 if (length 293 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 294 i = __i2c_read(data, length); 295 296 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 297 298 if (i == length) 299 return 0; 300 301 return -1; 302 } 303 304 int 305 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 306 { 307 int i = -1; /* signal error */ 308 u8 *a = (u8*)&addr; 309 310 if (i2c_wait4bus() >= 0 311 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 312 && __i2c_write(&a[4 - alen], alen) == alen) { 313 i = __i2c_write(data, length); 314 } 315 316 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 317 318 if (i == length) 319 return 0; 320 321 return -1; 322 } 323 324 int 325 i2c_probe(uchar chip) 326 { 327 /* For unknow reason the controller will ACK when 328 * probing for a slave with the same address, so skip 329 * it. 330 */ 331 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 332 return -1; 333 334 return i2c_read(chip, 0, 0, NULL, 0); 335 } 336 337 uchar 338 i2c_reg_read(uchar i2c_addr, uchar reg) 339 { 340 uchar buf[1]; 341 342 i2c_read(i2c_addr, reg, 1, buf, 1); 343 344 return buf[0]; 345 } 346 347 void 348 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) 349 { 350 i2c_write(i2c_addr, reg, 1, &val, 1); 351 } 352 353 int i2c_set_bus_num(unsigned int bus) 354 { 355 #ifdef CFG_I2C2_OFFSET 356 if (bus > 1) { 357 #else 358 if (bus > 0) { 359 #endif 360 return -1; 361 } 362 363 i2c_bus_num = bus; 364 365 return 0; 366 } 367 368 int i2c_set_bus_speed(unsigned int speed) 369 { 370 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 371 372 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 373 i2c_bus_speed[i2c_bus_num] = 374 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 375 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 376 377 return 0; 378 } 379 380 unsigned int i2c_get_bus_num(void) 381 { 382 return i2c_bus_num; 383 } 384 385 unsigned int i2c_get_bus_speed(void) 386 { 387 return i2c_bus_speed[i2c_bus_num]; 388 } 389 390 #endif /* CONFIG_HARD_I2C */ 391 #endif /* CONFIG_FSL_I2C */ 392