1 /* 2 * Copyright 2006,2009 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 /* The maximum number of microseconds we will wait until another master has 30 * released the bus. If not defined in the board header file, then use a 31 * generic value. 32 */ 33 #ifndef CONFIG_I2C_MBB_TIMEOUT 34 #define CONFIG_I2C_MBB_TIMEOUT 100000 35 #endif 36 37 /* The maximum number of microseconds we will wait for a read or write 38 * operation to complete. If not defined in the board header file, then use a 39 * generic value. 40 */ 41 #ifndef CONFIG_I2C_TIMEOUT 42 #define CONFIG_I2C_TIMEOUT 10000 43 #endif 44 45 #define I2C_READ_BIT 1 46 #define I2C_WRITE_BIT 0 47 48 DECLARE_GLOBAL_DATA_PTR; 49 50 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 51 * Default is bus 0. This is necessary because the DDR initialization 52 * runs from ROM, and we can't switch buses because we can't modify 53 * the global variables. 54 */ 55 #ifndef CONFIG_SYS_SPD_BUS_NUM 56 #define CONFIG_SYS_SPD_BUS_NUM 0 57 #endif 58 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; 59 #if defined(CONFIG_I2C_MUX) 60 static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; 61 #endif 62 63 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; 64 65 static const struct fsl_i2c *i2c_dev[2] = { 66 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), 67 #ifdef CONFIG_SYS_I2C2_OFFSET 68 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) 69 #endif 70 }; 71 72 /* I2C speed map for a DFSR value of 1 */ 73 74 /* 75 * Map I2C frequency dividers to FDR and DFSR values 76 * 77 * This structure is used to define the elements of a table that maps I2C 78 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 79 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 80 * Sampling Rate (DFSR) registers. 81 * 82 * The actual table should be defined in the board file, and it must be called 83 * fsl_i2c_speed_map[]. 84 * 85 * The last entry of the table must have a value of {-1, X}, where X is same 86 * FDR/DFSR values as the second-to-last entry. This guarantees that any 87 * search through the array will always find a match. 88 * 89 * The values of the divider must be in increasing numerical order, i.e. 90 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 91 * 92 * For this table, the values are based on a value of 1 for the DFSR 93 * register. See the application note AN2919 "Determining the I2C Frequency 94 * Divider Ratio for SCL" 95 * 96 * ColdFire I2C frequency dividers for FDR values are different from 97 * PowerPC. The protocol to use the I2C module is still the same. 98 * A different table is defined and are based on MCF5xxx user manual. 99 * 100 */ 101 static const struct { 102 unsigned short divider; 103 u8 fdr; 104 } fsl_i2c_speed_map[] = { 105 #ifdef __M68K__ 106 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 107 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 108 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 109 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 110 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 111 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 112 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 113 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 114 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 115 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 116 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 117 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 118 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 119 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 120 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 121 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 122 {-1, 31} 123 #endif 124 }; 125 126 /** 127 * Set the I2C bus speed for a given I2C device 128 * 129 * @param dev: the I2C device 130 * @i2c_clk: I2C bus clock frequency 131 * @speed: the desired speed of the bus 132 * 133 * The I2C device must be stopped before calling this function. 134 * 135 * The return value is the actual bus speed that is set. 136 */ 137 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 138 unsigned int i2c_clk, unsigned int speed) 139 { 140 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 141 142 /* 143 * We want to choose an FDR/DFSR that generates an I2C bus speed that 144 * is equal to or lower than the requested speed. That means that we 145 * want the first divider that is equal to or greater than the 146 * calculated divider. 147 */ 148 #ifdef __PPC__ 149 u8 dfsr, fdr = 0x31; /* Default if no FDR found */ 150 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ 151 unsigned short a, b, ga, gb; 152 unsigned long c_div, est_div; 153 154 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR 155 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; 156 #else 157 /* Condition 1: dfsr <= 50/T */ 158 dfsr = (5 * (i2c_clk / 1000)) / 100000; 159 #endif 160 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR 161 fdr = CONFIG_FSL_I2C_CUSTOM_FDR; 162 speed = i2c_clk / divider; /* Fake something */ 163 #else 164 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk); 165 if (!dfsr) 166 dfsr = 1; 167 168 est_div = ~0; 169 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { 170 for (gb = 0; gb < 8; gb++) { 171 b = 16 << gb; 172 c_div = b * (a + ((3*dfsr)/b)*2); 173 if ((c_div > divider) && (c_div < est_div)) { 174 unsigned short bin_gb, bin_ga; 175 176 est_div = c_div; 177 bin_gb = gb << 2; 178 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); 179 fdr = bin_gb | bin_ga; 180 speed = i2c_clk / est_div; 181 debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, " 182 "a:%d, b:%d, speed:%d\n", 183 fdr, est_div, ga, gb, a, b, speed); 184 /* Condition 2 not accounted for */ 185 debug("Tr <= %d ns\n", 186 (b - 3 * dfsr) * 1000000 / 187 (i2c_clk / 1000)); 188 } 189 } 190 if (a == 20) 191 a += 2; 192 if (a == 24) 193 a += 4; 194 } 195 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); 196 debug("FDR:0x%.2x, speed:%d\n", fdr, speed); 197 #endif 198 writeb(dfsr, &dev->dfsrr); /* set default filter */ 199 writeb(fdr, &dev->fdr); /* set bus speed */ 200 #else 201 unsigned int i; 202 203 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 204 if (fsl_i2c_speed_map[i].divider >= divider) { 205 u8 fdr; 206 207 fdr = fsl_i2c_speed_map[i].fdr; 208 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 209 writeb(fdr, &dev->fdr); /* set bus speed */ 210 211 break; 212 } 213 #endif 214 return speed; 215 } 216 217 void 218 i2c_init(int speed, int slaveadd) 219 { 220 struct fsl_i2c *dev; 221 unsigned int temp; 222 223 #ifdef CONFIG_SYS_I2C_INIT_BOARD 224 /* call board specific i2c bus reset routine before accessing the */ 225 /* environment, which might be in a chip on that bus. For details */ 226 /* about this problem see doc/I2C_Edge_Conditions. */ 227 i2c_init_board(); 228 #endif 229 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); 230 231 writeb(0, &dev->cr); /* stop I2C controller */ 232 udelay(5); /* let it shutdown in peace */ 233 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 234 if (gd->flags & GD_FLG_RELOC) 235 i2c_bus_speed[0] = temp; 236 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 237 writeb(0x0, &dev->sr); /* clear status register */ 238 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 239 240 #ifdef CONFIG_SYS_I2C2_OFFSET 241 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); 242 243 writeb(0, &dev->cr); /* stop I2C controller */ 244 udelay(5); /* let it shutdown in peace */ 245 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 246 if (gd->flags & GD_FLG_RELOC) 247 i2c_bus_speed[1] = temp; 248 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 249 writeb(0x0, &dev->sr); /* clear status register */ 250 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 251 #endif 252 } 253 254 static int 255 i2c_wait4bus(void) 256 { 257 unsigned long long timeval = get_ticks(); 258 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); 259 260 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 261 if ((get_ticks() - timeval) > timeout) 262 return -1; 263 } 264 265 return 0; 266 } 267 268 static __inline__ int 269 i2c_wait(int write) 270 { 271 u32 csr; 272 unsigned long long timeval = get_ticks(); 273 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); 274 275 do { 276 csr = readb(&i2c_dev[i2c_bus_num]->sr); 277 if (!(csr & I2C_SR_MIF)) 278 continue; 279 /* Read again to allow register to stabilise */ 280 csr = readb(&i2c_dev[i2c_bus_num]->sr); 281 282 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 283 284 if (csr & I2C_SR_MAL) { 285 debug("i2c_wait: MAL\n"); 286 return -1; 287 } 288 289 if (!(csr & I2C_SR_MCF)) { 290 debug("i2c_wait: unfinished\n"); 291 return -1; 292 } 293 294 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 295 debug("i2c_wait: No RXACK\n"); 296 return -1; 297 } 298 299 return 0; 300 } while ((get_ticks() - timeval) < timeout); 301 302 debug("i2c_wait: timed out\n"); 303 return -1; 304 } 305 306 static __inline__ int 307 i2c_write_addr (u8 dev, u8 dir, int rsta) 308 { 309 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 310 | (rsta ? I2C_CR_RSTA : 0), 311 &i2c_dev[i2c_bus_num]->cr); 312 313 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 314 315 if (i2c_wait(I2C_WRITE_BIT) < 0) 316 return 0; 317 318 return 1; 319 } 320 321 static __inline__ int 322 __i2c_write(u8 *data, int length) 323 { 324 int i; 325 326 for (i = 0; i < length; i++) { 327 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 328 329 if (i2c_wait(I2C_WRITE_BIT) < 0) 330 break; 331 } 332 333 return i; 334 } 335 336 static __inline__ int 337 __i2c_read(u8 *data, int length) 338 { 339 int i; 340 341 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 342 &i2c_dev[i2c_bus_num]->cr); 343 344 /* dummy read */ 345 readb(&i2c_dev[i2c_bus_num]->dr); 346 347 for (i = 0; i < length; i++) { 348 if (i2c_wait(I2C_READ_BIT) < 0) 349 break; 350 351 /* Generate ack on last next to last byte */ 352 if (i == length - 2) 353 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 354 &i2c_dev[i2c_bus_num]->cr); 355 356 /* Do not generate stop on last byte */ 357 if (i == length - 1) 358 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 359 &i2c_dev[i2c_bus_num]->cr); 360 361 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 362 } 363 364 return i; 365 } 366 367 int 368 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 369 { 370 int i = -1; /* signal error */ 371 u8 *a = (u8*)&addr; 372 373 if (i2c_wait4bus() >= 0 374 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 375 && __i2c_write(&a[4 - alen], alen) == alen) 376 i = 0; /* No error so far */ 377 378 if (length 379 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 380 i = __i2c_read(data, length); 381 382 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 383 384 if (i2c_wait4bus()) /* Wait until STOP */ 385 debug("i2c_read: wait4bus timed out\n"); 386 387 if (i == length) 388 return 0; 389 390 return -1; 391 } 392 393 int 394 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 395 { 396 int i = -1; /* signal error */ 397 u8 *a = (u8*)&addr; 398 399 if (i2c_wait4bus() >= 0 400 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 401 && __i2c_write(&a[4 - alen], alen) == alen) { 402 i = __i2c_write(data, length); 403 } 404 405 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 406 if (i2c_wait4bus()) /* Wait until STOP */ 407 debug("i2c_write: wait4bus timed out\n"); 408 409 if (i == length) 410 return 0; 411 412 return -1; 413 } 414 415 int 416 i2c_probe(uchar chip) 417 { 418 /* For unknow reason the controller will ACK when 419 * probing for a slave with the same address, so skip 420 * it. 421 */ 422 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 423 return -1; 424 425 return i2c_read(chip, 0, 0, NULL, 0); 426 } 427 428 int i2c_set_bus_num(unsigned int bus) 429 { 430 #if defined(CONFIG_I2C_MUX) 431 if (bus < CONFIG_SYS_MAX_I2C_BUS) { 432 i2c_bus_num = bus; 433 } else { 434 int ret; 435 436 ret = i2x_mux_select_mux(bus); 437 if (ret) 438 return ret; 439 i2c_bus_num = 0; 440 } 441 i2c_bus_num_mux = bus; 442 #else 443 #ifdef CONFIG_SYS_I2C2_OFFSET 444 if (bus > 1) { 445 #else 446 if (bus > 0) { 447 #endif 448 return -1; 449 } 450 451 i2c_bus_num = bus; 452 #endif 453 return 0; 454 } 455 456 int i2c_set_bus_speed(unsigned int speed) 457 { 458 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 459 460 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 461 i2c_bus_speed[i2c_bus_num] = 462 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 463 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 464 465 return 0; 466 } 467 468 unsigned int i2c_get_bus_num(void) 469 { 470 #if defined(CONFIG_I2C_MUX) 471 return i2c_bus_num_mux; 472 #else 473 return i2c_bus_num; 474 #endif 475 } 476 477 unsigned int i2c_get_bus_speed(void) 478 { 479 return i2c_bus_speed[i2c_bus_num]; 480 } 481 482 #endif /* CONFIG_HARD_I2C */ 483