1 /* 2 * Copyright 2006 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 #define I2C_TIMEOUT (CONFIG_SYS_HZ / 4) 30 31 #define I2C_READ_BIT 1 32 #define I2C_WRITE_BIT 0 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 37 * Default is bus 0. This is necessary because the DDR initialization 38 * runs from ROM, and we can't switch buses because we can't modify 39 * the global variables. 40 */ 41 #ifndef CONFIG_SYS_SPD_BUS_NUM 42 #define CONFIG_SYS_SPD_BUS_NUM 0 43 #endif 44 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; 45 #if defined(CONFIG_I2C_MUX) 46 static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; 47 #endif 48 49 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; 50 51 static const struct fsl_i2c *i2c_dev[2] = { 52 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), 53 #ifdef CONFIG_SYS_I2C2_OFFSET 54 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) 55 #endif 56 }; 57 58 /* I2C speed map for a DFSR value of 1 */ 59 60 /* 61 * Map I2C frequency dividers to FDR and DFSR values 62 * 63 * This structure is used to define the elements of a table that maps I2C 64 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 65 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 66 * Sampling Rate (DFSR) registers. 67 * 68 * The actual table should be defined in the board file, and it must be called 69 * fsl_i2c_speed_map[]. 70 * 71 * The last entry of the table must have a value of {-1, X}, where X is same 72 * FDR/DFSR values as the second-to-last entry. This guarantees that any 73 * search through the array will always find a match. 74 * 75 * The values of the divider must be in increasing numerical order, i.e. 76 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 77 * 78 * For this table, the values are based on a value of 1 for the DFSR 79 * register. See the application note AN2919 "Determining the I2C Frequency 80 * Divider Ratio for SCL" 81 * 82 * ColdFire I2C frequency dividers for FDR values are different from 83 * PowerPC. The protocol to use the I2C module is still the same. 84 * A different table is defined and are based on MCF5xxx user manual. 85 * 86 */ 87 static const struct { 88 unsigned short divider; 89 #ifdef __PPC__ 90 u8 dfsr; 91 #endif 92 u8 fdr; 93 } fsl_i2c_speed_map[] = { 94 #ifdef __PPC__ 95 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, 96 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, 97 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, 98 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, 99 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, 100 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, 101 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, 102 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, 103 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, 104 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, 105 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, 106 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, 107 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, 108 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, 109 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, 110 {61440, 1, 31}, {-1, 1, 31} 111 #elif defined(__M68K__) 112 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 113 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 114 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 115 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 116 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 117 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 118 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 119 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 120 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 121 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 122 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 123 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 124 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 125 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 126 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 127 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 128 {-1, 31} 129 #endif 130 }; 131 132 /** 133 * Set the I2C bus speed for a given I2C device 134 * 135 * @param dev: the I2C device 136 * @i2c_clk: I2C bus clock frequency 137 * @speed: the desired speed of the bus 138 * 139 * The I2C device must be stopped before calling this function. 140 * 141 * The return value is the actual bus speed that is set. 142 */ 143 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 144 unsigned int i2c_clk, unsigned int speed) 145 { 146 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 147 unsigned int i; 148 149 /* 150 * We want to choose an FDR/DFSR that generates an I2C bus speed that 151 * is equal to or lower than the requested speed. That means that we 152 * want the first divider that is equal to or greater than the 153 * calculated divider. 154 */ 155 156 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 157 if (fsl_i2c_speed_map[i].divider >= divider) { 158 u8 fdr; 159 #ifdef __PPC__ 160 u8 dfsr; 161 dfsr = fsl_i2c_speed_map[i].dfsr; 162 #endif 163 fdr = fsl_i2c_speed_map[i].fdr; 164 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 165 writeb(fdr, &dev->fdr); /* set bus speed */ 166 #ifdef __PPC__ 167 writeb(dfsr, &dev->dfsrr); /* set default filter */ 168 #endif 169 break; 170 } 171 172 return speed; 173 } 174 175 void 176 i2c_init(int speed, int slaveadd) 177 { 178 struct fsl_i2c *dev; 179 unsigned int temp; 180 181 #ifdef CONFIG_SYS_I2C_INIT_BOARD 182 /* call board specific i2c bus reset routine before accessing the */ 183 /* environment, which might be in a chip on that bus. For details */ 184 /* about this problem see doc/I2C_Edge_Conditions. */ 185 i2c_init_board(); 186 #endif 187 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); 188 189 writeb(0, &dev->cr); /* stop I2C controller */ 190 udelay(5); /* let it shutdown in peace */ 191 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 192 if (gd->flags & GD_FLG_RELOC) 193 i2c_bus_speed[0] = temp; 194 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 195 writeb(0x0, &dev->sr); /* clear status register */ 196 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 197 198 #ifdef CONFIG_SYS_I2C2_OFFSET 199 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); 200 201 writeb(0, &dev->cr); /* stop I2C controller */ 202 udelay(5); /* let it shutdown in peace */ 203 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 204 if (gd->flags & GD_FLG_RELOC) 205 i2c_bus_speed[1] = temp; 206 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 207 writeb(0x0, &dev->sr); /* clear status register */ 208 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 209 #endif 210 } 211 212 static __inline__ int 213 i2c_wait4bus(void) 214 { 215 unsigned long long timeval = get_ticks(); 216 217 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 218 if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT)) 219 return -1; 220 } 221 222 return 0; 223 } 224 225 static __inline__ int 226 i2c_wait(int write) 227 { 228 u32 csr; 229 unsigned long long timeval = get_ticks(); 230 231 do { 232 csr = readb(&i2c_dev[i2c_bus_num]->sr); 233 if (!(csr & I2C_SR_MIF)) 234 continue; 235 236 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 237 238 if (csr & I2C_SR_MAL) { 239 debug("i2c_wait: MAL\n"); 240 return -1; 241 } 242 243 if (!(csr & I2C_SR_MCF)) { 244 debug("i2c_wait: unfinished\n"); 245 return -1; 246 } 247 248 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 249 debug("i2c_wait: No RXACK\n"); 250 return -1; 251 } 252 253 return 0; 254 } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT)); 255 256 debug("i2c_wait: timed out\n"); 257 return -1; 258 } 259 260 static __inline__ int 261 i2c_write_addr (u8 dev, u8 dir, int rsta) 262 { 263 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 264 | (rsta ? I2C_CR_RSTA : 0), 265 &i2c_dev[i2c_bus_num]->cr); 266 267 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 268 269 if (i2c_wait(I2C_WRITE_BIT) < 0) 270 return 0; 271 272 return 1; 273 } 274 275 static __inline__ int 276 __i2c_write(u8 *data, int length) 277 { 278 int i; 279 280 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 281 &i2c_dev[i2c_bus_num]->cr); 282 283 for (i = 0; i < length; i++) { 284 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 285 286 if (i2c_wait(I2C_WRITE_BIT) < 0) 287 break; 288 } 289 290 return i; 291 } 292 293 static __inline__ int 294 __i2c_read(u8 *data, int length) 295 { 296 int i; 297 298 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 299 &i2c_dev[i2c_bus_num]->cr); 300 301 /* dummy read */ 302 readb(&i2c_dev[i2c_bus_num]->dr); 303 304 for (i = 0; i < length; i++) { 305 if (i2c_wait(I2C_READ_BIT) < 0) 306 break; 307 308 /* Generate ack on last next to last byte */ 309 if (i == length - 2) 310 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 311 &i2c_dev[i2c_bus_num]->cr); 312 313 /* Generate stop on last byte */ 314 if (i == length - 1) 315 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); 316 317 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 318 } 319 320 return i; 321 } 322 323 int 324 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 325 { 326 int i = -1; /* signal error */ 327 u8 *a = (u8*)&addr; 328 329 if (i2c_wait4bus() >= 0 330 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 331 && __i2c_write(&a[4 - alen], alen) == alen) 332 i = 0; /* No error so far */ 333 334 if (length 335 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 336 i = __i2c_read(data, length); 337 338 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 339 340 if (i == length) 341 return 0; 342 343 return -1; 344 } 345 346 int 347 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 348 { 349 int i = -1; /* signal error */ 350 u8 *a = (u8*)&addr; 351 352 if (i2c_wait4bus() >= 0 353 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 354 && __i2c_write(&a[4 - alen], alen) == alen) { 355 i = __i2c_write(data, length); 356 } 357 358 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 359 360 if (i == length) 361 return 0; 362 363 return -1; 364 } 365 366 int 367 i2c_probe(uchar chip) 368 { 369 /* For unknow reason the controller will ACK when 370 * probing for a slave with the same address, so skip 371 * it. 372 */ 373 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 374 return -1; 375 376 return i2c_read(chip, 0, 0, NULL, 0); 377 } 378 379 int i2c_set_bus_num(unsigned int bus) 380 { 381 #if defined(CONFIG_I2C_MUX) 382 if (bus < CONFIG_SYS_MAX_I2C_BUS) { 383 i2c_bus_num = bus; 384 } else { 385 int ret; 386 387 ret = i2x_mux_select_mux(bus); 388 if (ret) 389 return ret; 390 i2c_bus_num = 0; 391 } 392 i2c_bus_num_mux = bus; 393 #else 394 #ifdef CONFIG_SYS_I2C2_OFFSET 395 if (bus > 1) { 396 #else 397 if (bus > 0) { 398 #endif 399 return -1; 400 } 401 402 i2c_bus_num = bus; 403 #endif 404 return 0; 405 } 406 407 int i2c_set_bus_speed(unsigned int speed) 408 { 409 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 410 411 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 412 i2c_bus_speed[i2c_bus_num] = 413 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 414 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 415 416 return 0; 417 } 418 419 unsigned int i2c_get_bus_num(void) 420 { 421 #if defined(CONFIG_I2C_MUX) 422 return i2c_bus_num_mux; 423 #else 424 return i2c_bus_num; 425 #endif 426 } 427 428 unsigned int i2c_get_bus_speed(void) 429 { 430 return i2c_bus_speed[i2c_bus_num]; 431 } 432 433 #endif /* CONFIG_HARD_I2C */ 434