xref: /openbmc/u-boot/drivers/i2c/fsl_i2c.c (revision 746f985a)
1 /*
2  * Copyright 2006,2009 Freescale Semiconductor, Inc.
3  *
4  * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
5  * Changes for multibus/multiadapter I2C support.
6  *
7  * SPDX-License-Identifier:	GPL-2.0
8  */
9 
10 #include <common.h>
11 #include <command.h>
12 #include <i2c.h>		/* Functional interface */
13 #include <asm/io.h>
14 #include <asm/fsl_i2c.h>	/* HW definitions */
15 
16 /* The maximum number of microseconds we will wait until another master has
17  * released the bus.  If not defined in the board header file, then use a
18  * generic value.
19  */
20 #ifndef CONFIG_I2C_MBB_TIMEOUT
21 #define CONFIG_I2C_MBB_TIMEOUT	100000
22 #endif
23 
24 /* The maximum number of microseconds we will wait for a read or write
25  * operation to complete.  If not defined in the board header file, then use a
26  * generic value.
27  */
28 #ifndef CONFIG_I2C_TIMEOUT
29 #define CONFIG_I2C_TIMEOUT	100000
30 #endif
31 
32 #define I2C_READ_BIT  1
33 #define I2C_WRITE_BIT 0
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 static const struct fsl_i2c *i2c_dev[4] = {
38 	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
39 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
40 	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
41 #endif
42 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
43 	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
44 #endif
45 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
46 	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
47 #endif
48 };
49 
50 /* I2C speed map for a DFSR value of 1 */
51 
52 /*
53  * Map I2C frequency dividers to FDR and DFSR values
54  *
55  * This structure is used to define the elements of a table that maps I2C
56  * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
57  * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
58  * Sampling Rate (DFSR) registers.
59  *
60  * The actual table should be defined in the board file, and it must be called
61  * fsl_i2c_speed_map[].
62  *
63  * The last entry of the table must have a value of {-1, X}, where X is same
64  * FDR/DFSR values as the second-to-last entry.  This guarantees that any
65  * search through the array will always find a match.
66  *
67  * The values of the divider must be in increasing numerical order, i.e.
68  * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
69  *
70  * For this table, the values are based on a value of 1 for the DFSR
71  * register.  See the application note AN2919 "Determining the I2C Frequency
72  * Divider Ratio for SCL"
73  *
74  * ColdFire I2C frequency dividers for FDR values are different from
75  * PowerPC. The protocol to use the I2C module is still the same.
76  * A different table is defined and are based on MCF5xxx user manual.
77  *
78  */
79 static const struct {
80 	unsigned short divider;
81 	u8 fdr;
82 } fsl_i2c_speed_map[] = {
83 #ifdef __M68K__
84 	{20, 32}, {22, 33}, {24, 34}, {26, 35},
85 	{28, 0}, {28, 36}, {30, 1}, {32, 37},
86 	{34, 2}, {36, 38}, {40, 3}, {40, 39},
87 	{44, 4}, {48, 5}, {48, 40}, {56, 6},
88 	{56, 41}, {64, 42}, {68, 7}, {72, 43},
89 	{80, 8}, {80, 44}, {88, 9}, {96, 41},
90 	{104, 10}, {112, 42}, {128, 11}, {128, 43},
91 	{144, 12}, {160, 13}, {160, 48}, {192, 14},
92 	{192, 49}, {224, 50}, {240, 15}, {256, 51},
93 	{288, 16}, {320, 17}, {320, 52}, {384, 18},
94 	{384, 53}, {448, 54}, {480, 19}, {512, 55},
95 	{576, 20}, {640, 21}, {640, 56}, {768, 22},
96 	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
97 	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
98 	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
99 	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
100 	{-1, 31}
101 #endif
102 };
103 
104 /**
105  * Set the I2C bus speed for a given I2C device
106  *
107  * @param dev: the I2C device
108  * @i2c_clk: I2C bus clock frequency
109  * @speed: the desired speed of the bus
110  *
111  * The I2C device must be stopped before calling this function.
112  *
113  * The return value is the actual bus speed that is set.
114  */
115 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
116 	unsigned int i2c_clk, unsigned int speed)
117 {
118 	unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
119 
120 	/*
121 	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
122 	 * is equal to or lower than the requested speed.  That means that we
123 	 * want the first divider that is equal to or greater than the
124 	 * calculated divider.
125 	 */
126 #ifdef __PPC__
127 	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
128 	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
129 	unsigned short a, b, ga, gb;
130 	unsigned long c_div, est_div;
131 
132 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
133 	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
134 #else
135 	/* Condition 1: dfsr <= 50/T */
136 	dfsr = (5 * (i2c_clk / 1000)) / 100000;
137 #endif
138 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
139 	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
140 	speed = i2c_clk / divider; /* Fake something */
141 #else
142 	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
143 	if (!dfsr)
144 		dfsr = 1;
145 
146 	est_div = ~0;
147 	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
148 		for (gb = 0; gb < 8; gb++) {
149 			b = 16 << gb;
150 			c_div = b * (a + ((3*dfsr)/b)*2);
151 			if ((c_div > divider) && (c_div < est_div)) {
152 				unsigned short bin_gb, bin_ga;
153 
154 				est_div = c_div;
155 				bin_gb = gb << 2;
156 				bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
157 				fdr = bin_gb | bin_ga;
158 				speed = i2c_clk / est_div;
159 				debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
160 				      "a:%d, b:%d, speed:%d\n",
161 				      fdr, est_div, ga, gb, a, b, speed);
162 				/* Condition 2 not accounted for */
163 				debug("Tr <= %d ns\n",
164 				      (b - 3 * dfsr) * 1000000 /
165 				      (i2c_clk / 1000));
166 			}
167 		}
168 		if (a == 20)
169 			a += 2;
170 		if (a == 24)
171 			a += 4;
172 	}
173 	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
174 	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
175 #endif
176 	writeb(dfsr, &dev->dfsrr);	/* set default filter */
177 	writeb(fdr, &dev->fdr);		/* set bus speed */
178 #else
179 	unsigned int i;
180 
181 	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
182 		if (fsl_i2c_speed_map[i].divider >= divider) {
183 			u8 fdr;
184 
185 			fdr = fsl_i2c_speed_map[i].fdr;
186 			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
187 			writeb(fdr, &dev->fdr);		/* set bus speed */
188 
189 			break;
190 		}
191 #endif
192 	return speed;
193 }
194 
195 static unsigned int get_i2c_clock(int bus)
196 {
197 	if (bus)
198 		return gd->arch.i2c2_clk;	/* I2C2 clock */
199 	else
200 		return gd->arch.i2c1_clk;	/* I2C1 clock */
201 }
202 
203 static int fsl_i2c_fixup(const struct fsl_i2c *dev)
204 {
205 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
206 	unsigned long long timeval = 0;
207 	int ret = -1;
208 	unsigned int flags = 0;
209 
210 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
211 	unsigned int svr = get_svr();
212 	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
213 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
214 		flags = I2C_CR_BIT6;
215 #endif
216 
217 	writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
218 
219 	timeval = get_ticks();
220 	while (!(readb(&dev->sr) & I2C_SR_MBB)) {
221 		if ((get_ticks() - timeval) > timeout)
222 			goto err;
223 	}
224 
225 	if (readb(&dev->sr) & I2C_SR_MAL) {
226 		/* SDA is stuck low */
227 		writeb(0, &dev->cr);
228 		udelay(100);
229 		writeb(I2C_CR_MSTA | flags, &dev->cr);
230 		writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
231 	}
232 
233 	readb(&dev->dr);
234 
235 	timeval = get_ticks();
236 	while (!(readb(&dev->sr) & I2C_SR_MIF)) {
237 		if ((get_ticks() - timeval) > timeout)
238 			goto err;
239 	}
240 	ret = 0;
241 
242 err:
243 	writeb(I2C_CR_MEN | flags, &dev->cr);
244 	writeb(0, &dev->sr);
245 	udelay(100);
246 
247 	return ret;
248 }
249 
250 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
251 {
252 	const struct fsl_i2c *dev;
253 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
254 	unsigned long long timeval;
255 
256 #ifdef CONFIG_SYS_I2C_INIT_BOARD
257 	/* Call board specific i2c bus reset routine before accessing the
258 	 * environment, which might be in a chip on that bus. For details
259 	 * about this problem see doc/I2C_Edge_Conditions.
260 	*/
261 	i2c_init_board();
262 #endif
263 	dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
264 
265 	writeb(0, &dev->cr);		/* stop I2C controller */
266 	udelay(5);			/* let it shutdown in peace */
267 	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
268 	writeb(slaveadd << 1, &dev->adr);/* write slave address */
269 	writeb(0x0, &dev->sr);		/* clear status register */
270 	writeb(I2C_CR_MEN, &dev->cr);	/* start I2C controller */
271 
272 	timeval = get_ticks();
273 	while (readb(&dev->sr) & I2C_SR_MBB) {
274 		if ((get_ticks() - timeval) < timeout)
275 			continue;
276 
277 		if (fsl_i2c_fixup(dev))
278 			debug("i2c_init: BUS#%d failed to init\n",
279 			      adap->hwadapnr);
280 
281 		break;
282 	}
283 
284 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
285 	/* Call board specific i2c bus reset routine AFTER the bus has been
286 	 * initialized. Use either this callpoint or i2c_init_board;
287 	 * which is called before i2c_init operations.
288 	 * For details about this problem see doc/I2C_Edge_Conditions.
289 	*/
290 	i2c_board_late_init();
291 #endif
292 }
293 
294 static int
295 i2c_wait4bus(struct i2c_adapter *adap)
296 {
297 	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
298 	unsigned long long timeval = get_ticks();
299 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
300 
301 	while (readb(&dev->sr) & I2C_SR_MBB) {
302 		if ((get_ticks() - timeval) > timeout)
303 			return -1;
304 	}
305 
306 	return 0;
307 }
308 
309 static __inline__ int
310 i2c_wait(struct i2c_adapter *adap, int write)
311 {
312 	u32 csr;
313 	unsigned long long timeval = get_ticks();
314 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
315 	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
316 
317 	do {
318 		csr = readb(&dev->sr);
319 		if (!(csr & I2C_SR_MIF))
320 			continue;
321 		/* Read again to allow register to stabilise */
322 		csr = readb(&dev->sr);
323 
324 		writeb(0x0, &dev->sr);
325 
326 		if (csr & I2C_SR_MAL) {
327 			debug("i2c_wait: MAL\n");
328 			return -1;
329 		}
330 
331 		if (!(csr & I2C_SR_MCF))	{
332 			debug("i2c_wait: unfinished\n");
333 			return -1;
334 		}
335 
336 		if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
337 			debug("i2c_wait: No RXACK\n");
338 			return -1;
339 		}
340 
341 		return 0;
342 	} while ((get_ticks() - timeval) < timeout);
343 
344 	debug("i2c_wait: timed out\n");
345 	return -1;
346 }
347 
348 static __inline__ int
349 i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
350 {
351 	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
352 
353 	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
354 	       | (rsta ? I2C_CR_RSTA : 0),
355 	       &device->cr);
356 
357 	writeb((dev << 1) | dir, &device->dr);
358 
359 	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
360 		return 0;
361 
362 	return 1;
363 }
364 
365 static __inline__ int
366 __i2c_write(struct i2c_adapter *adap, u8 *data, int length)
367 {
368 	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
369 	int i;
370 
371 	for (i = 0; i < length; i++) {
372 		writeb(data[i], &dev->dr);
373 
374 		if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
375 			break;
376 	}
377 
378 	return i;
379 }
380 
381 static __inline__ int
382 __i2c_read(struct i2c_adapter *adap, u8 *data, int length)
383 {
384 	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
385 	int i;
386 
387 	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
388 	       &dev->cr);
389 
390 	/* dummy read */
391 	readb(&dev->dr);
392 
393 	for (i = 0; i < length; i++) {
394 		if (i2c_wait(adap, I2C_READ_BIT) < 0)
395 			break;
396 
397 		/* Generate ack on last next to last byte */
398 		if (i == length - 2)
399 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
400 			       &dev->cr);
401 
402 		/* Do not generate stop on last byte */
403 		if (i == length - 1)
404 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
405 			       &dev->cr);
406 
407 		data[i] = readb(&dev->dr);
408 	}
409 
410 	return i;
411 }
412 
413 static int
414 fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
415 	     int length)
416 {
417 	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
418 	int i = -1; /* signal error */
419 	u8 *a = (u8*)&addr;
420 	int len = alen * -1;
421 
422 	if (i2c_wait4bus(adap) < 0)
423 		return -1;
424 
425 	/* To handle the need of I2C devices that require to write few bytes
426 	 * (more than 4 bytes of address as in the case of else part)
427 	 * of data before reading, Negative equivalent of length(bytes to write)
428 	 * is passed, but used the +ve part of len for writing data
429 	 */
430 	if (alen < 0) {
431 		/* Generate a START and send the Address and
432 		 * the Tx Bytes to the slave.
433 		 * "START: Address: Write bytes data[len]"
434 		 * IF part supports writing any number of bytes in contrast
435 		 * to the else part, which supports writing address offset
436 		 * of upto 4 bytes only.
437 		 * bytes that need to be written are passed in
438 		 * "data", which will eventually keep the data READ,
439 		 * after writing the len bytes out of it
440 		 */
441 		if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
442 			i = __i2c_write(adap, data, len);
443 
444 		if (i != len)
445 			return -1;
446 
447 		if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
448 			i = __i2c_read(adap, data, length);
449 	} else {
450 		if ((!length || alen > 0) &&
451 		    i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0  &&
452 		    __i2c_write(adap, &a[4 - alen], alen) == alen)
453 			i = 0; /* No error so far */
454 
455 		if (length &&
456 		    i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
457 			i = __i2c_read(adap, data, length);
458 	}
459 
460 	writeb(I2C_CR_MEN, &device->cr);
461 
462 	if (i2c_wait4bus(adap)) /* Wait until STOP */
463 		debug("i2c_read: wait4bus timed out\n");
464 
465 	if (i == length)
466 	    return 0;
467 
468 	return -1;
469 }
470 
471 static int
472 fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
473 	      u8 *data, int length)
474 {
475 	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
476 	int i = -1; /* signal error */
477 	u8 *a = (u8*)&addr;
478 
479 	if (i2c_wait4bus(adap) < 0)
480 		return -1;
481 
482 	if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
483 	    __i2c_write(adap, &a[4 - alen], alen) == alen) {
484 		i = __i2c_write(adap, data, length);
485 	}
486 
487 	writeb(I2C_CR_MEN, &device->cr);
488 	if (i2c_wait4bus(adap)) /* Wait until STOP */
489 		debug("i2c_write: wait4bus timed out\n");
490 
491 	if (i == length)
492 	    return 0;
493 
494 	return -1;
495 }
496 
497 static int
498 fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
499 {
500 	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
501 	/* For unknow reason the controller will ACK when
502 	 * probing for a slave with the same address, so skip
503 	 * it.
504 	 */
505 	if (chip == (readb(&dev->adr) >> 1))
506 		return -1;
507 
508 	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
509 }
510 
511 static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
512 			unsigned int speed)
513 {
514 	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
515 
516 	writeb(0, &dev->cr);		/* stop controller */
517 	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
518 	writeb(I2C_CR_MEN, &dev->cr);	/* start controller */
519 
520 	return 0;
521 }
522 
523 /*
524  * Register fsl i2c adapters
525  */
526 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
527 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
528 			 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
529 			 0)
530 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
531 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
532 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
533 			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
534 			 1)
535 #endif
536 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
537 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
538 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
539 			 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
540 			 2)
541 #endif
542 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
543 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
544 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
545 			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
546 			 3)
547 #endif
548