1 /* 2 * Copyright 2006 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 #define I2C_TIMEOUT (CONFIG_SYS_HZ / 4) 30 31 #define I2C_READ_BIT 1 32 #define I2C_WRITE_BIT 0 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 37 * Default is bus 0. This is necessary because the DDR initialization 38 * runs from ROM, and we can't switch buses because we can't modify 39 * the global variables. 40 */ 41 #ifdef CONFIG_SYS_SPD_BUS_NUM 42 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CONFIG_SYS_SPD_BUS_NUM; 43 #else 44 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; 45 #endif 46 47 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; 48 49 static const struct fsl_i2c *i2c_dev[2] = { 50 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), 51 #ifdef CONFIG_SYS_I2C2_OFFSET 52 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) 53 #endif 54 }; 55 56 /* I2C speed map for a DFSR value of 1 */ 57 58 /* 59 * Map I2C frequency dividers to FDR and DFSR values 60 * 61 * This structure is used to define the elements of a table that maps I2C 62 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 63 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 64 * Sampling Rate (DFSR) registers. 65 * 66 * The actual table should be defined in the board file, and it must be called 67 * fsl_i2c_speed_map[]. 68 * 69 * The last entry of the table must have a value of {-1, X}, where X is same 70 * FDR/DFSR values as the second-to-last entry. This guarantees that any 71 * search through the array will always find a match. 72 * 73 * The values of the divider must be in increasing numerical order, i.e. 74 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 75 * 76 * For this table, the values are based on a value of 1 for the DFSR 77 * register. See the application note AN2919 "Determining the I2C Frequency 78 * Divider Ratio for SCL" 79 * 80 * ColdFire I2C frequency dividers for FDR values are different from 81 * PowerPC. The protocol to use the I2C module is still the same. 82 * A different table is defined and are based on MCF5xxx user manual. 83 * 84 */ 85 static const struct { 86 unsigned short divider; 87 #ifdef __PPC__ 88 u8 dfsr; 89 #endif 90 u8 fdr; 91 } fsl_i2c_speed_map[] = { 92 #ifdef __PPC__ 93 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, 94 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, 95 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, 96 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, 97 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, 98 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, 99 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, 100 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, 101 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, 102 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, 103 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, 104 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, 105 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, 106 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, 107 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, 108 {61440, 1, 31}, {-1, 1, 31} 109 #elif defined(__M68K__) 110 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 111 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 112 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 113 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 114 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 115 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 116 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 117 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 118 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 119 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 120 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 121 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 122 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 123 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 124 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 125 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 126 {-1, 31} 127 #endif 128 }; 129 130 /** 131 * Set the I2C bus speed for a given I2C device 132 * 133 * @param dev: the I2C device 134 * @i2c_clk: I2C bus clock frequency 135 * @speed: the desired speed of the bus 136 * 137 * The I2C device must be stopped before calling this function. 138 * 139 * The return value is the actual bus speed that is set. 140 */ 141 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 142 unsigned int i2c_clk, unsigned int speed) 143 { 144 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 145 unsigned int i; 146 147 /* 148 * We want to choose an FDR/DFSR that generates an I2C bus speed that 149 * is equal to or lower than the requested speed. That means that we 150 * want the first divider that is equal to or greater than the 151 * calculated divider. 152 */ 153 154 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 155 if (fsl_i2c_speed_map[i].divider >= divider) { 156 u8 fdr; 157 #ifdef __PPC__ 158 u8 dfsr; 159 dfsr = fsl_i2c_speed_map[i].dfsr; 160 #endif 161 fdr = fsl_i2c_speed_map[i].fdr; 162 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 163 writeb(fdr, &dev->fdr); /* set bus speed */ 164 #ifdef __PPC__ 165 writeb(dfsr, &dev->dfsrr); /* set default filter */ 166 #endif 167 break; 168 } 169 170 return speed; 171 } 172 173 void 174 i2c_init(int speed, int slaveadd) 175 { 176 struct fsl_i2c *dev; 177 unsigned int temp; 178 179 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); 180 181 writeb(0, &dev->cr); /* stop I2C controller */ 182 udelay(5); /* let it shutdown in peace */ 183 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 184 if (gd->flags & GD_FLG_RELOC) 185 i2c_bus_speed[0] = temp; 186 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 187 writeb(0x0, &dev->sr); /* clear status register */ 188 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 189 190 #ifdef CONFIG_SYS_I2C2_OFFSET 191 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); 192 193 writeb(0, &dev->cr); /* stop I2C controller */ 194 udelay(5); /* let it shutdown in peace */ 195 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 196 if (gd->flags & GD_FLG_RELOC) 197 i2c_bus_speed[1] = temp; 198 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 199 writeb(0x0, &dev->sr); /* clear status register */ 200 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 201 #endif 202 } 203 204 static __inline__ int 205 i2c_wait4bus(void) 206 { 207 unsigned long long timeval = get_ticks(); 208 209 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 210 if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT)) 211 return -1; 212 } 213 214 return 0; 215 } 216 217 static __inline__ int 218 i2c_wait(int write) 219 { 220 u32 csr; 221 unsigned long long timeval = get_ticks(); 222 223 do { 224 csr = readb(&i2c_dev[i2c_bus_num]->sr); 225 if (!(csr & I2C_SR_MIF)) 226 continue; 227 228 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 229 230 if (csr & I2C_SR_MAL) { 231 debug("i2c_wait: MAL\n"); 232 return -1; 233 } 234 235 if (!(csr & I2C_SR_MCF)) { 236 debug("i2c_wait: unfinished\n"); 237 return -1; 238 } 239 240 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 241 debug("i2c_wait: No RXACK\n"); 242 return -1; 243 } 244 245 return 0; 246 } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT)); 247 248 debug("i2c_wait: timed out\n"); 249 return -1; 250 } 251 252 static __inline__ int 253 i2c_write_addr (u8 dev, u8 dir, int rsta) 254 { 255 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 256 | (rsta ? I2C_CR_RSTA : 0), 257 &i2c_dev[i2c_bus_num]->cr); 258 259 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 260 261 if (i2c_wait(I2C_WRITE_BIT) < 0) 262 return 0; 263 264 return 1; 265 } 266 267 static __inline__ int 268 __i2c_write(u8 *data, int length) 269 { 270 int i; 271 272 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 273 &i2c_dev[i2c_bus_num]->cr); 274 275 for (i = 0; i < length; i++) { 276 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 277 278 if (i2c_wait(I2C_WRITE_BIT) < 0) 279 break; 280 } 281 282 return i; 283 } 284 285 static __inline__ int 286 __i2c_read(u8 *data, int length) 287 { 288 int i; 289 290 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 291 &i2c_dev[i2c_bus_num]->cr); 292 293 /* dummy read */ 294 readb(&i2c_dev[i2c_bus_num]->dr); 295 296 for (i = 0; i < length; i++) { 297 if (i2c_wait(I2C_READ_BIT) < 0) 298 break; 299 300 /* Generate ack on last next to last byte */ 301 if (i == length - 2) 302 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 303 &i2c_dev[i2c_bus_num]->cr); 304 305 /* Generate stop on last byte */ 306 if (i == length - 1) 307 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); 308 309 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 310 } 311 312 return i; 313 } 314 315 int 316 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 317 { 318 int i = -1; /* signal error */ 319 u8 *a = (u8*)&addr; 320 321 if (i2c_wait4bus() >= 0 322 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 323 && __i2c_write(&a[4 - alen], alen) == alen) 324 i = 0; /* No error so far */ 325 326 if (length 327 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 328 i = __i2c_read(data, length); 329 330 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 331 332 if (i == length) 333 return 0; 334 335 return -1; 336 } 337 338 int 339 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 340 { 341 int i = -1; /* signal error */ 342 u8 *a = (u8*)&addr; 343 344 if (i2c_wait4bus() >= 0 345 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 346 && __i2c_write(&a[4 - alen], alen) == alen) { 347 i = __i2c_write(data, length); 348 } 349 350 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 351 352 if (i == length) 353 return 0; 354 355 return -1; 356 } 357 358 int 359 i2c_probe(uchar chip) 360 { 361 /* For unknow reason the controller will ACK when 362 * probing for a slave with the same address, so skip 363 * it. 364 */ 365 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 366 return -1; 367 368 return i2c_read(chip, 0, 0, NULL, 0); 369 } 370 371 uchar 372 i2c_reg_read(uchar i2c_addr, uchar reg) 373 { 374 uchar buf[1]; 375 376 i2c_read(i2c_addr, reg, 1, buf, 1); 377 378 return buf[0]; 379 } 380 381 void 382 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) 383 { 384 i2c_write(i2c_addr, reg, 1, &val, 1); 385 } 386 387 int i2c_set_bus_num(unsigned int bus) 388 { 389 #ifdef CONFIG_SYS_I2C2_OFFSET 390 if (bus > 1) { 391 #else 392 if (bus > 0) { 393 #endif 394 return -1; 395 } 396 397 i2c_bus_num = bus; 398 399 return 0; 400 } 401 402 int i2c_set_bus_speed(unsigned int speed) 403 { 404 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 405 406 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 407 i2c_bus_speed[i2c_bus_num] = 408 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 409 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 410 411 return 0; 412 } 413 414 unsigned int i2c_get_bus_num(void) 415 { 416 return i2c_bus_num; 417 } 418 419 unsigned int i2c_get_bus_speed(void) 420 { 421 return i2c_bus_speed[i2c_bus_num]; 422 } 423 424 #endif /* CONFIG_HARD_I2C */ 425