xref: /openbmc/u-boot/drivers/i2c/fsl_i2c.c (revision 53193a4f)
1 /*
2  * Copyright 2006,2009 Freescale Semiconductor, Inc.
3  *
4  * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
5  * Changes for multibus/multiadapter I2C support.
6  *
7  * SPDX-License-Identifier:	GPL-2.0
8  */
9 
10 #include <common.h>
11 #include <command.h>
12 #include <i2c.h>		/* Functional interface */
13 #include <asm/io.h>
14 #include <asm/fsl_i2c.h>	/* HW definitions */
15 #include <dm.h>
16 #include <mapmem.h>
17 
18 /* The maximum number of microseconds we will wait until another master has
19  * released the bus.  If not defined in the board header file, then use a
20  * generic value.
21  */
22 #ifndef CONFIG_I2C_MBB_TIMEOUT
23 #define CONFIG_I2C_MBB_TIMEOUT	100000
24 #endif
25 
26 /* The maximum number of microseconds we will wait for a read or write
27  * operation to complete.  If not defined in the board header file, then use a
28  * generic value.
29  */
30 #ifndef CONFIG_I2C_TIMEOUT
31 #define CONFIG_I2C_TIMEOUT	100000
32 #endif
33 
34 #define I2C_READ_BIT  1
35 #define I2C_WRITE_BIT 0
36 
37 DECLARE_GLOBAL_DATA_PTR;
38 
39 #ifndef CONFIG_DM_I2C
40 static const struct fsl_i2c_base *i2c_base[4] = {
41 	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
42 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
43 	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
44 #endif
45 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
46 	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
47 #endif
48 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
49 	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
50 #endif
51 };
52 #endif
53 
54 /* I2C speed map for a DFSR value of 1 */
55 
56 #ifdef __M68K__
57 /*
58  * Map I2C frequency dividers to FDR and DFSR values
59  *
60  * This structure is used to define the elements of a table that maps I2C
61  * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
62  * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
63  * Sampling Rate (DFSR) registers.
64  *
65  * The actual table should be defined in the board file, and it must be called
66  * fsl_i2c_speed_map[].
67  *
68  * The last entry of the table must have a value of {-1, X}, where X is same
69  * FDR/DFSR values as the second-to-last entry.  This guarantees that any
70  * search through the array will always find a match.
71  *
72  * The values of the divider must be in increasing numerical order, i.e.
73  * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
74  *
75  * For this table, the values are based on a value of 1 for the DFSR
76  * register.  See the application note AN2919 "Determining the I2C Frequency
77  * Divider Ratio for SCL"
78  *
79  * ColdFire I2C frequency dividers for FDR values are different from
80  * PowerPC. The protocol to use the I2C module is still the same.
81  * A different table is defined and are based on MCF5xxx user manual.
82  *
83  */
84 static const struct {
85 	unsigned short divider;
86 	u8 fdr;
87 } fsl_i2c_speed_map[] = {
88 	{20, 32}, {22, 33}, {24, 34}, {26, 35},
89 	{28, 0}, {28, 36}, {30, 1}, {32, 37},
90 	{34, 2}, {36, 38}, {40, 3}, {40, 39},
91 	{44, 4}, {48, 5}, {48, 40}, {56, 6},
92 	{56, 41}, {64, 42}, {68, 7}, {72, 43},
93 	{80, 8}, {80, 44}, {88, 9}, {96, 41},
94 	{104, 10}, {112, 42}, {128, 11}, {128, 43},
95 	{144, 12}, {160, 13}, {160, 48}, {192, 14},
96 	{192, 49}, {224, 50}, {240, 15}, {256, 51},
97 	{288, 16}, {320, 17}, {320, 52}, {384, 18},
98 	{384, 53}, {448, 54}, {480, 19}, {512, 55},
99 	{576, 20}, {640, 21}, {640, 56}, {768, 22},
100 	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
101 	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
102 	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
103 	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
104 	{-1, 31}
105 };
106 #endif
107 
108 /**
109  * Set the I2C bus speed for a given I2C device
110  *
111  * @param base: the I2C device registers
112  * @i2c_clk: I2C bus clock frequency
113  * @speed: the desired speed of the bus
114  *
115  * The I2C device must be stopped before calling this function.
116  *
117  * The return value is the actual bus speed that is set.
118  */
119 static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
120 	unsigned int i2c_clk, unsigned int speed)
121 {
122 	unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
123 
124 	/*
125 	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
126 	 * is equal to or lower than the requested speed.  That means that we
127 	 * want the first divider that is equal to or greater than the
128 	 * calculated divider.
129 	 */
130 #ifdef __PPC__
131 	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
132 	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
133 	unsigned short a, b, ga, gb;
134 	unsigned long c_div, est_div;
135 
136 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
137 	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
138 #else
139 	/* Condition 1: dfsr <= 50/T */
140 	dfsr = (5 * (i2c_clk / 1000)) / 100000;
141 #endif
142 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
143 	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
144 	speed = i2c_clk / divider; /* Fake something */
145 #else
146 	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
147 	if (!dfsr)
148 		dfsr = 1;
149 
150 	est_div = ~0;
151 	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
152 		for (gb = 0; gb < 8; gb++) {
153 			b = 16 << gb;
154 			c_div = b * (a + ((3*dfsr)/b)*2);
155 			if ((c_div > divider) && (c_div < est_div)) {
156 				unsigned short bin_gb, bin_ga;
157 
158 				est_div = c_div;
159 				bin_gb = gb << 2;
160 				bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
161 				fdr = bin_gb | bin_ga;
162 				speed = i2c_clk / est_div;
163 				debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
164 				      "a:%d, b:%d, speed:%d\n",
165 				      fdr, est_div, ga, gb, a, b, speed);
166 				/* Condition 2 not accounted for */
167 				debug("Tr <= %d ns\n",
168 				      (b - 3 * dfsr) * 1000000 /
169 				      (i2c_clk / 1000));
170 			}
171 		}
172 		if (a == 20)
173 			a += 2;
174 		if (a == 24)
175 			a += 4;
176 	}
177 	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
178 	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
179 #endif
180 	writeb(dfsr, &base->dfsrr);	/* set default filter */
181 	writeb(fdr, &base->fdr);	/* set bus speed */
182 #else
183 	unsigned int i;
184 
185 	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
186 		if (fsl_i2c_speed_map[i].divider >= divider) {
187 			u8 fdr;
188 
189 			fdr = fsl_i2c_speed_map[i].fdr;
190 			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
191 			writeb(fdr, &base->fdr);	/* set bus speed */
192 
193 			break;
194 		}
195 #endif
196 	return speed;
197 }
198 
199 #ifndef CONFIG_DM_I2C
200 static unsigned int get_i2c_clock(int bus)
201 {
202 	if (bus)
203 		return gd->arch.i2c2_clk;	/* I2C2 clock */
204 	else
205 		return gd->arch.i2c1_clk;	/* I2C1 clock */
206 }
207 #endif
208 
209 static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
210 {
211 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
212 	unsigned long long timeval = 0;
213 	int ret = -1;
214 	unsigned int flags = 0;
215 
216 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
217 	unsigned int svr = get_svr();
218 	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
219 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
220 		flags = I2C_CR_BIT6;
221 #endif
222 
223 	writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
224 
225 	timeval = get_ticks();
226 	while (!(readb(&base->sr) & I2C_SR_MBB)) {
227 		if ((get_ticks() - timeval) > timeout)
228 			goto err;
229 	}
230 
231 	if (readb(&base->sr) & I2C_SR_MAL) {
232 		/* SDA is stuck low */
233 		writeb(0, &base->cr);
234 		udelay(100);
235 		writeb(I2C_CR_MSTA | flags, &base->cr);
236 		writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
237 	}
238 
239 	readb(&base->dr);
240 
241 	timeval = get_ticks();
242 	while (!(readb(&base->sr) & I2C_SR_MIF)) {
243 		if ((get_ticks() - timeval) > timeout)
244 			goto err;
245 	}
246 	ret = 0;
247 
248 err:
249 	writeb(I2C_CR_MEN | flags, &base->cr);
250 	writeb(0, &base->sr);
251 	udelay(100);
252 
253 	return ret;
254 }
255 
256 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
257 		       slaveadd, int i2c_clk, int busnum)
258 {
259 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
260 	unsigned long long timeval;
261 
262 #ifdef CONFIG_SYS_I2C_INIT_BOARD
263 	/* Call board specific i2c bus reset routine before accessing the
264 	 * environment, which might be in a chip on that bus. For details
265 	 * about this problem see doc/I2C_Edge_Conditions.
266 	*/
267 	i2c_init_board();
268 #endif
269 	writeb(0, &base->cr);		/* stop I2C controller */
270 	udelay(5);			/* let it shutdown in peace */
271 	set_i2c_bus_speed(base, i2c_clk, speed);
272 	writeb(slaveadd << 1, &base->adr);/* write slave address */
273 	writeb(0x0, &base->sr);		/* clear status register */
274 	writeb(I2C_CR_MEN, &base->cr);	/* start I2C controller */
275 
276 	timeval = get_ticks();
277 	while (readb(&base->sr) & I2C_SR_MBB) {
278 		if ((get_ticks() - timeval) < timeout)
279 			continue;
280 
281 		if (fsl_i2c_fixup(base))
282 			debug("i2c_init: BUS#%d failed to init\n",
283 			      busnum);
284 
285 		break;
286 	}
287 }
288 
289 static int
290 i2c_wait4bus(const struct fsl_i2c_base *base)
291 {
292 	unsigned long long timeval = get_ticks();
293 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
294 
295 	while (readb(&base->sr) & I2C_SR_MBB) {
296 		if ((get_ticks() - timeval) > timeout)
297 			return -1;
298 	}
299 
300 	return 0;
301 }
302 
303 static inline int
304 i2c_wait(const struct fsl_i2c_base *base, int write)
305 {
306 	u32 csr;
307 	unsigned long long timeval = get_ticks();
308 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
309 
310 	do {
311 		csr = readb(&base->sr);
312 		if (!(csr & I2C_SR_MIF))
313 			continue;
314 		/* Read again to allow register to stabilise */
315 		csr = readb(&base->sr);
316 
317 		writeb(0x0, &base->sr);
318 
319 		if (csr & I2C_SR_MAL) {
320 			debug("i2c_wait: MAL\n");
321 			return -1;
322 		}
323 
324 		if (!(csr & I2C_SR_MCF))	{
325 			debug("i2c_wait: unfinished\n");
326 			return -1;
327 		}
328 
329 		if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
330 			debug("i2c_wait: No RXACK\n");
331 			return -1;
332 		}
333 
334 		return 0;
335 	} while ((get_ticks() - timeval) < timeout);
336 
337 	debug("i2c_wait: timed out\n");
338 	return -1;
339 }
340 
341 static inline int
342 i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta)
343 {
344 	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
345 	       | (rsta ? I2C_CR_RSTA : 0),
346 	       &base->cr);
347 
348 	writeb((dev << 1) | dir, &base->dr);
349 
350 	if (i2c_wait(base, I2C_WRITE_BIT) < 0)
351 		return 0;
352 
353 	return 1;
354 }
355 
356 static inline int
357 __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length)
358 {
359 	int i;
360 
361 	for (i = 0; i < length; i++) {
362 		writeb(data[i], &base->dr);
363 
364 		if (i2c_wait(base, I2C_WRITE_BIT) < 0)
365 			break;
366 	}
367 
368 	return i;
369 }
370 
371 static inline int
372 __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length)
373 {
374 	int i;
375 
376 	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
377 	       &base->cr);
378 
379 	/* dummy read */
380 	readb(&base->dr);
381 
382 	for (i = 0; i < length; i++) {
383 		if (i2c_wait(base, I2C_READ_BIT) < 0)
384 			break;
385 
386 		/* Generate ack on last next to last byte */
387 		if (i == length - 2)
388 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
389 			       &base->cr);
390 
391 		/* Do not generate stop on last byte */
392 		if (i == length - 1)
393 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
394 			       &base->cr);
395 
396 		data[i] = readb(&base->dr);
397 	}
398 
399 	return i;
400 }
401 
402 static int
403 __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
404 	   u8 *data, int dlen)
405 {
406 	int ret = -1; /* signal error */
407 
408 	if (i2c_wait4bus(base) < 0)
409 		return -1;
410 
411 	/* Some drivers use offset lengths in excess of 4 bytes. These drivers
412 	 * adhere to the following convention:
413 	 * - the offset length is passed as negative (that is, the absolute
414 	 *   value of olen is the actual offset length)
415 	 * - the offset itself is passed in data, which is overwritten by the
416 	 *   subsequent read operation
417 	 */
418 	if (olen < 0) {
419 		if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
420 			ret = __i2c_write_data(base, data, -olen);
421 
422 		if (ret != -olen)
423 			return -1;
424 
425 		if (dlen && i2c_write_addr(base, chip_addr,
426 					   I2C_READ_BIT, 1) != 0)
427 			ret = __i2c_read_data(base, data, dlen);
428 	} else {
429 		if ((!dlen || olen > 0) &&
430 		    i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
431 		    __i2c_write_data(base, offset, olen) == olen)
432 			ret = 0; /* No error so far */
433 
434 		if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
435 					   olen ? 1 : 0) != 0)
436 			ret = __i2c_read_data(base, data, dlen);
437 	}
438 
439 	writeb(I2C_CR_MEN, &base->cr);
440 
441 	if (i2c_wait4bus(base)) /* Wait until STOP */
442 		debug("i2c_read: wait4bus timed out\n");
443 
444 	if (ret == dlen)
445 		return 0;
446 
447 	return -1;
448 }
449 
450 static int
451 __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
452 	    u8 *data, int dlen)
453 {
454 	int ret = -1; /* signal error */
455 
456 	if (i2c_wait4bus(base) < 0)
457 		return -1;
458 
459 	if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
460 	    __i2c_write_data(base, offset, olen) == olen) {
461 		ret = __i2c_write_data(base, data, dlen);
462 	}
463 
464 	writeb(I2C_CR_MEN, &base->cr);
465 	if (i2c_wait4bus(base)) /* Wait until STOP */
466 		debug("i2c_write: wait4bus timed out\n");
467 
468 	if (ret == dlen)
469 		return 0;
470 
471 	return -1;
472 }
473 
474 static int
475 __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
476 {
477 	/* For unknow reason the controller will ACK when
478 	 * probing for a slave with the same address, so skip
479 	 * it.
480 	 */
481 	if (chip == (readb(&base->adr) >> 1))
482 		return -1;
483 
484 	return __i2c_read(base, chip, 0, 0, NULL, 0);
485 }
486 
487 static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base,
488 			unsigned int speed, int i2c_clk)
489 {
490 	writeb(0, &base->cr);		/* stop controller */
491 	set_i2c_bus_speed(base, i2c_clk, speed);
492 	writeb(I2C_CR_MEN, &base->cr);	/* start controller */
493 
494 	return 0;
495 }
496 
497 #ifndef CONFIG_DM_I2C
498 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
499 {
500 	__i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
501 		   get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
502 }
503 
504 static int
505 fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
506 {
507 	return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
508 }
509 
510 static int
511 fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
512 	     u8 *data, int dlen)
513 {
514 	u8 *o = (u8 *)&offset;
515 	return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
516 			  olen, data, dlen);
517 }
518 
519 static int
520 fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
521 	      u8 *data, int dlen)
522 {
523 	u8 *o = (u8 *)&offset;
524 	return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
525 			   olen, data, dlen);
526 }
527 
528 static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
529 					  unsigned int speed)
530 {
531 	return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
532 				   get_i2c_clock(adap->hwadapnr));
533 }
534 
535 /*
536  * Register fsl i2c adapters
537  */
538 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
539 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
540 			 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
541 			 0)
542 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
543 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
544 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
545 			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
546 			 1)
547 #endif
548 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
549 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
550 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
551 			 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
552 			 2)
553 #endif
554 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
555 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
556 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
557 			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
558 			 3)
559 #endif
560 #else /* CONFIG_DM_I2C */
561 static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
562 			      u32 chip_flags)
563 {
564 	struct fsl_i2c_dev *dev = dev_get_priv(bus);
565 	return __i2c_probe_chip(dev->base, chip_addr);
566 }
567 
568 static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
569 {
570 	struct fsl_i2c_dev *dev = dev_get_priv(bus);
571 	return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
572 }
573 
574 static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
575 {
576 	struct fsl_i2c_dev *dev = dev_get_priv(bus);
577 	fdt_addr_t addr;
578 	fdt_size_t size;
579 	int node = dev_of_offset(bus);
580 
581 	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, node, "reg", 0,
582 						  &size, false);
583 
584 	dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
585 
586 	if (!dev->base)
587 		return -ENOMEM;
588 
589 	dev->index = fdtdec_get_int(gd->fdt_blob, node, "cell-index", -1);
590 	dev->slaveadd = fdtdec_get_int(gd->fdt_blob, node,
591 				       "u-boot,i2c-slave-addr", 0x7f);
592 	dev->speed = fdtdec_get_int(gd->fdt_blob, node, "clock-frequency",
593 				    400000);
594 
595 	dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
596 
597 	return 0;
598 }
599 
600 static int fsl_i2c_probe(struct udevice *bus)
601 {
602 	struct fsl_i2c_dev *dev = dev_get_priv(bus);
603 	__i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
604 		   dev->index);
605 	return 0;
606 }
607 
608 static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
609 {
610 	struct fsl_i2c_dev *dev = dev_get_priv(bus);
611 	struct i2c_msg *dmsg, *omsg, dummy;
612 
613 	memset(&dummy, 0, sizeof(struct i2c_msg));
614 
615 	/* We expect either two messages (one with an offset and one with the
616 	 * actucal data) or one message (just data) */
617 	if (nmsgs > 2 || nmsgs == 0) {
618 		debug("%s: Only one or two messages are supported.", __func__);
619 		return -1;
620 	}
621 
622 	omsg = nmsgs == 1 ? &dummy : msg;
623 	dmsg = nmsgs == 1 ? msg : msg + 1;
624 
625 	if (dmsg->flags & I2C_M_RD)
626 		return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
627 				  dmsg->buf, dmsg->len);
628 	else
629 		return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
630 				   dmsg->buf, dmsg->len);
631 }
632 
633 static const struct dm_i2c_ops fsl_i2c_ops = {
634 	.xfer           = fsl_i2c_xfer,
635 	.probe_chip     = fsl_i2c_probe_chip,
636 	.set_bus_speed  = fsl_i2c_set_bus_speed,
637 };
638 
639 static const struct udevice_id fsl_i2c_ids[] = {
640 	{ .compatible = "fsl-i2c", },
641 	{ /* sentinel */ }
642 };
643 
644 U_BOOT_DRIVER(i2c_fsl) = {
645 	.name = "i2c_fsl",
646 	.id = UCLASS_I2C,
647 	.of_match = fsl_i2c_ids,
648 	.probe = fsl_i2c_probe,
649 	.ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
650 	.priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
651 	.ops = &fsl_i2c_ops,
652 };
653 
654 #endif /* CONFIG_DM_I2C */
655