1 /* 2 * Copyright 2006 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 #define I2C_TIMEOUT (CONFIG_SYS_HZ / 4) 30 31 #define I2C_READ_BIT 1 32 #define I2C_WRITE_BIT 0 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 37 * Default is bus 0. This is necessary because the DDR initialization 38 * runs from ROM, and we can't switch buses because we can't modify 39 * the global variables. 40 */ 41 #ifndef CONFIG_SYS_SPD_BUS_NUM 42 #define CONFIG_SYS_SPD_BUS_NUM 0 43 #endif 44 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; 45 46 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; 47 48 static const struct fsl_i2c *i2c_dev[2] = { 49 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), 50 #ifdef CONFIG_SYS_I2C2_OFFSET 51 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) 52 #endif 53 }; 54 55 /* I2C speed map for a DFSR value of 1 */ 56 57 /* 58 * Map I2C frequency dividers to FDR and DFSR values 59 * 60 * This structure is used to define the elements of a table that maps I2C 61 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 62 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 63 * Sampling Rate (DFSR) registers. 64 * 65 * The actual table should be defined in the board file, and it must be called 66 * fsl_i2c_speed_map[]. 67 * 68 * The last entry of the table must have a value of {-1, X}, where X is same 69 * FDR/DFSR values as the second-to-last entry. This guarantees that any 70 * search through the array will always find a match. 71 * 72 * The values of the divider must be in increasing numerical order, i.e. 73 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 74 * 75 * For this table, the values are based on a value of 1 for the DFSR 76 * register. See the application note AN2919 "Determining the I2C Frequency 77 * Divider Ratio for SCL" 78 * 79 * ColdFire I2C frequency dividers for FDR values are different from 80 * PowerPC. The protocol to use the I2C module is still the same. 81 * A different table is defined and are based on MCF5xxx user manual. 82 * 83 */ 84 static const struct { 85 unsigned short divider; 86 #ifdef __PPC__ 87 u8 dfsr; 88 #endif 89 u8 fdr; 90 } fsl_i2c_speed_map[] = { 91 #ifdef __PPC__ 92 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, 93 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, 94 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, 95 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, 96 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, 97 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, 98 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, 99 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, 100 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, 101 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, 102 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, 103 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, 104 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, 105 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, 106 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, 107 {61440, 1, 31}, {-1, 1, 31} 108 #elif defined(__M68K__) 109 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 110 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 111 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 112 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 113 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 114 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 115 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 116 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 117 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 118 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 119 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 120 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 121 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 122 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 123 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 124 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 125 {-1, 31} 126 #endif 127 }; 128 129 /** 130 * Set the I2C bus speed for a given I2C device 131 * 132 * @param dev: the I2C device 133 * @i2c_clk: I2C bus clock frequency 134 * @speed: the desired speed of the bus 135 * 136 * The I2C device must be stopped before calling this function. 137 * 138 * The return value is the actual bus speed that is set. 139 */ 140 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 141 unsigned int i2c_clk, unsigned int speed) 142 { 143 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 144 unsigned int i; 145 146 /* 147 * We want to choose an FDR/DFSR that generates an I2C bus speed that 148 * is equal to or lower than the requested speed. That means that we 149 * want the first divider that is equal to or greater than the 150 * calculated divider. 151 */ 152 153 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 154 if (fsl_i2c_speed_map[i].divider >= divider) { 155 u8 fdr; 156 #ifdef __PPC__ 157 u8 dfsr; 158 dfsr = fsl_i2c_speed_map[i].dfsr; 159 #endif 160 fdr = fsl_i2c_speed_map[i].fdr; 161 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 162 writeb(fdr, &dev->fdr); /* set bus speed */ 163 #ifdef __PPC__ 164 writeb(dfsr, &dev->dfsrr); /* set default filter */ 165 #endif 166 break; 167 } 168 169 return speed; 170 } 171 172 void 173 i2c_init(int speed, int slaveadd) 174 { 175 struct fsl_i2c *dev; 176 unsigned int temp; 177 178 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); 179 180 writeb(0, &dev->cr); /* stop I2C controller */ 181 udelay(5); /* let it shutdown in peace */ 182 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 183 if (gd->flags & GD_FLG_RELOC) 184 i2c_bus_speed[0] = temp; 185 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 186 writeb(0x0, &dev->sr); /* clear status register */ 187 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 188 189 #ifdef CONFIG_SYS_I2C2_OFFSET 190 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); 191 192 writeb(0, &dev->cr); /* stop I2C controller */ 193 udelay(5); /* let it shutdown in peace */ 194 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 195 if (gd->flags & GD_FLG_RELOC) 196 i2c_bus_speed[1] = temp; 197 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 198 writeb(0x0, &dev->sr); /* clear status register */ 199 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 200 #endif 201 } 202 203 static __inline__ int 204 i2c_wait4bus(void) 205 { 206 unsigned long long timeval = get_ticks(); 207 208 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 209 if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT)) 210 return -1; 211 } 212 213 return 0; 214 } 215 216 static __inline__ int 217 i2c_wait(int write) 218 { 219 u32 csr; 220 unsigned long long timeval = get_ticks(); 221 222 do { 223 csr = readb(&i2c_dev[i2c_bus_num]->sr); 224 if (!(csr & I2C_SR_MIF)) 225 continue; 226 227 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 228 229 if (csr & I2C_SR_MAL) { 230 debug("i2c_wait: MAL\n"); 231 return -1; 232 } 233 234 if (!(csr & I2C_SR_MCF)) { 235 debug("i2c_wait: unfinished\n"); 236 return -1; 237 } 238 239 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 240 debug("i2c_wait: No RXACK\n"); 241 return -1; 242 } 243 244 return 0; 245 } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT)); 246 247 debug("i2c_wait: timed out\n"); 248 return -1; 249 } 250 251 static __inline__ int 252 i2c_write_addr (u8 dev, u8 dir, int rsta) 253 { 254 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 255 | (rsta ? I2C_CR_RSTA : 0), 256 &i2c_dev[i2c_bus_num]->cr); 257 258 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 259 260 if (i2c_wait(I2C_WRITE_BIT) < 0) 261 return 0; 262 263 return 1; 264 } 265 266 static __inline__ int 267 __i2c_write(u8 *data, int length) 268 { 269 int i; 270 271 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 272 &i2c_dev[i2c_bus_num]->cr); 273 274 for (i = 0; i < length; i++) { 275 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 276 277 if (i2c_wait(I2C_WRITE_BIT) < 0) 278 break; 279 } 280 281 return i; 282 } 283 284 static __inline__ int 285 __i2c_read(u8 *data, int length) 286 { 287 int i; 288 289 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 290 &i2c_dev[i2c_bus_num]->cr); 291 292 /* dummy read */ 293 readb(&i2c_dev[i2c_bus_num]->dr); 294 295 for (i = 0; i < length; i++) { 296 if (i2c_wait(I2C_READ_BIT) < 0) 297 break; 298 299 /* Generate ack on last next to last byte */ 300 if (i == length - 2) 301 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 302 &i2c_dev[i2c_bus_num]->cr); 303 304 /* Generate stop on last byte */ 305 if (i == length - 1) 306 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); 307 308 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 309 } 310 311 return i; 312 } 313 314 int 315 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 316 { 317 int i = -1; /* signal error */ 318 u8 *a = (u8*)&addr; 319 320 if (i2c_wait4bus() >= 0 321 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 322 && __i2c_write(&a[4 - alen], alen) == alen) 323 i = 0; /* No error so far */ 324 325 if (length 326 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 327 i = __i2c_read(data, length); 328 329 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 330 331 if (i == length) 332 return 0; 333 334 return -1; 335 } 336 337 int 338 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 339 { 340 int i = -1; /* signal error */ 341 u8 *a = (u8*)&addr; 342 343 if (i2c_wait4bus() >= 0 344 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 345 && __i2c_write(&a[4 - alen], alen) == alen) { 346 i = __i2c_write(data, length); 347 } 348 349 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 350 351 if (i == length) 352 return 0; 353 354 return -1; 355 } 356 357 int 358 i2c_probe(uchar chip) 359 { 360 /* For unknow reason the controller will ACK when 361 * probing for a slave with the same address, so skip 362 * it. 363 */ 364 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 365 return -1; 366 367 return i2c_read(chip, 0, 0, NULL, 0); 368 } 369 370 int i2c_set_bus_num(unsigned int bus) 371 { 372 #ifdef CONFIG_SYS_I2C2_OFFSET 373 if (bus > 1) { 374 #else 375 if (bus > 0) { 376 #endif 377 return -1; 378 } 379 380 i2c_bus_num = bus; 381 382 return 0; 383 } 384 385 int i2c_set_bus_speed(unsigned int speed) 386 { 387 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 388 389 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 390 i2c_bus_speed[i2c_bus_num] = 391 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 392 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 393 394 return 0; 395 } 396 397 unsigned int i2c_get_bus_num(void) 398 { 399 return i2c_bus_num; 400 } 401 402 unsigned int i2c_get_bus_speed(void) 403 { 404 return i2c_bus_speed[i2c_bus_num]; 405 } 406 407 #endif /* CONFIG_HARD_I2C */ 408