1 /* 2 * Copyright 2006 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 #define I2C_TIMEOUT (CFG_HZ / 4) 30 31 #define I2C_READ_BIT 1 32 #define I2C_WRITE_BIT 0 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 37 * Default is bus 0. This is necessary because the DDR initialization 38 * runs from ROM, and we can't switch buses because we can't modify 39 * the global variables. 40 */ 41 #ifdef CFG_SPD_BUS_NUM 42 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; 43 #else 44 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; 45 #endif 46 47 static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED}; 48 49 static const struct fsl_i2c *i2c_dev[2] = { 50 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), 51 #ifdef CFG_I2C2_OFFSET 52 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) 53 #endif 54 }; 55 56 /* I2C speed map for a DFSR value of 1 */ 57 58 /* 59 * Map I2C frequency dividers to FDR and DFSR values 60 * 61 * This structure is used to define the elements of a table that maps I2C 62 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 63 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 64 * Sampling Rate (DFSR) registers. 65 * 66 * The actual table should be defined in the board file, and it must be called 67 * fsl_i2c_speed_map[]. 68 * 69 * The last entry of the table must have a value of {-1, X}, where X is same 70 * FDR/DFSR values as the second-to-last entry. This guarantees that any 71 * search through the array will always find a match. 72 * 73 * The values of the divider must be in increasing numerical order, i.e. 74 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 75 * 76 * For this table, the values are based on a value of 1 for the DFSR 77 * register. See the application note AN2919 "Determining the I2C Frequency 78 * Divider Ratio for SCL" 79 */ 80 static const struct { 81 unsigned short divider; 82 u8 dfsr; 83 u8 fdr; 84 } fsl_i2c_speed_map[] = { 85 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, 86 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, 87 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, 88 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, 89 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, 90 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, 91 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, 92 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, 93 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, 94 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, 95 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, 96 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, 97 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, 98 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, 99 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, 100 {61440, 1, 31}, {-1, 1, 31} 101 }; 102 103 /** 104 * Set the I2C bus speed for a given I2C device 105 * 106 * @param dev: the I2C device 107 * @i2c_clk: I2C bus clock frequency 108 * @speed: the desired speed of the bus 109 * 110 * The I2C device must be stopped before calling this function. 111 * 112 * The return value is the actual bus speed that is set. 113 */ 114 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 115 unsigned int i2c_clk, unsigned int speed) 116 { 117 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 118 unsigned int i; 119 120 /* 121 * We want to choose an FDR/DFSR that generates an I2C bus speed that 122 * is equal to or lower than the requested speed. That means that we 123 * want the first divider that is equal to or greater than the 124 * calculated divider. 125 */ 126 127 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 128 if (fsl_i2c_speed_map[i].divider >= divider) { 129 u8 fdr, dfsr; 130 dfsr = fsl_i2c_speed_map[i].dfsr; 131 fdr = fsl_i2c_speed_map[i].fdr; 132 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 133 writeb(fdr, &dev->fdr); /* set bus speed */ 134 writeb(dfsr, &dev->dfsrr); /* set default filter */ 135 break; 136 } 137 138 return speed; 139 } 140 141 void 142 i2c_init(int speed, int slaveadd) 143 { 144 struct fsl_i2c *dev; 145 unsigned int temp; 146 147 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); 148 149 writeb(0, &dev->cr); /* stop I2C controller */ 150 udelay(5); /* let it shutdown in peace */ 151 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 152 if (gd->flags & GD_FLG_RELOC) 153 i2c_bus_speed[0] = temp; 154 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 155 writeb(0x0, &dev->sr); /* clear status register */ 156 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 157 158 #ifdef CFG_I2C2_OFFSET 159 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); 160 161 writeb(0, &dev->cr); /* stop I2C controller */ 162 udelay(5); /* let it shutdown in peace */ 163 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 164 if (gd->flags & GD_FLG_RELOC) 165 i2c_bus_speed[1] = temp; 166 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 167 writeb(0x0, &dev->sr); /* clear status register */ 168 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 169 #endif 170 } 171 172 static __inline__ int 173 i2c_wait4bus(void) 174 { 175 unsigned long long timeval = get_ticks(); 176 177 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 178 if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT)) 179 return -1; 180 } 181 182 return 0; 183 } 184 185 static __inline__ int 186 i2c_wait(int write) 187 { 188 u32 csr; 189 unsigned long long timeval = get_ticks(); 190 191 do { 192 csr = readb(&i2c_dev[i2c_bus_num]->sr); 193 if (!(csr & I2C_SR_MIF)) 194 continue; 195 196 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 197 198 if (csr & I2C_SR_MAL) { 199 debug("i2c_wait: MAL\n"); 200 return -1; 201 } 202 203 if (!(csr & I2C_SR_MCF)) { 204 debug("i2c_wait: unfinished\n"); 205 return -1; 206 } 207 208 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 209 debug("i2c_wait: No RXACK\n"); 210 return -1; 211 } 212 213 return 0; 214 } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT)); 215 216 debug("i2c_wait: timed out\n"); 217 return -1; 218 } 219 220 static __inline__ int 221 i2c_write_addr (u8 dev, u8 dir, int rsta) 222 { 223 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 224 | (rsta ? I2C_CR_RSTA : 0), 225 &i2c_dev[i2c_bus_num]->cr); 226 227 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 228 229 if (i2c_wait(I2C_WRITE_BIT) < 0) 230 return 0; 231 232 return 1; 233 } 234 235 static __inline__ int 236 __i2c_write(u8 *data, int length) 237 { 238 int i; 239 240 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 241 &i2c_dev[i2c_bus_num]->cr); 242 243 for (i = 0; i < length; i++) { 244 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 245 246 if (i2c_wait(I2C_WRITE_BIT) < 0) 247 break; 248 } 249 250 return i; 251 } 252 253 static __inline__ int 254 __i2c_read(u8 *data, int length) 255 { 256 int i; 257 258 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 259 &i2c_dev[i2c_bus_num]->cr); 260 261 /* dummy read */ 262 readb(&i2c_dev[i2c_bus_num]->dr); 263 264 for (i = 0; i < length; i++) { 265 if (i2c_wait(I2C_READ_BIT) < 0) 266 break; 267 268 /* Generate ack on last next to last byte */ 269 if (i == length - 2) 270 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 271 &i2c_dev[i2c_bus_num]->cr); 272 273 /* Generate stop on last byte */ 274 if (i == length - 1) 275 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); 276 277 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 278 } 279 280 return i; 281 } 282 283 int 284 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 285 { 286 int i = -1; /* signal error */ 287 u8 *a = (u8*)&addr; 288 289 if (i2c_wait4bus() >= 0 290 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 291 && __i2c_write(&a[4 - alen], alen) == alen) 292 i = 0; /* No error so far */ 293 294 if (length 295 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 296 i = __i2c_read(data, length); 297 298 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 299 300 if (i == length) 301 return 0; 302 303 return -1; 304 } 305 306 int 307 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 308 { 309 int i = -1; /* signal error */ 310 u8 *a = (u8*)&addr; 311 312 if (i2c_wait4bus() >= 0 313 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 314 && __i2c_write(&a[4 - alen], alen) == alen) { 315 i = __i2c_write(data, length); 316 } 317 318 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 319 320 if (i == length) 321 return 0; 322 323 return -1; 324 } 325 326 int 327 i2c_probe(uchar chip) 328 { 329 /* For unknow reason the controller will ACK when 330 * probing for a slave with the same address, so skip 331 * it. 332 */ 333 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 334 return -1; 335 336 return i2c_read(chip, 0, 0, NULL, 0); 337 } 338 339 uchar 340 i2c_reg_read(uchar i2c_addr, uchar reg) 341 { 342 uchar buf[1]; 343 344 i2c_read(i2c_addr, reg, 1, buf, 1); 345 346 return buf[0]; 347 } 348 349 void 350 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) 351 { 352 i2c_write(i2c_addr, reg, 1, &val, 1); 353 } 354 355 int i2c_set_bus_num(unsigned int bus) 356 { 357 #ifdef CFG_I2C2_OFFSET 358 if (bus > 1) { 359 #else 360 if (bus > 0) { 361 #endif 362 return -1; 363 } 364 365 i2c_bus_num = bus; 366 367 return 0; 368 } 369 370 int i2c_set_bus_speed(unsigned int speed) 371 { 372 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 373 374 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 375 i2c_bus_speed[i2c_bus_num] = 376 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 377 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 378 379 return 0; 380 } 381 382 unsigned int i2c_get_bus_num(void) 383 { 384 return i2c_bus_num; 385 } 386 387 unsigned int i2c_get_bus_speed(void) 388 { 389 return i2c_bus_speed[i2c_bus_num]; 390 } 391 392 #endif /* CONFIG_HARD_I2C */ 393