1 /* 2 * Copyright 2006,2009 Freescale Semiconductor, Inc. 3 * 4 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 * Changes for multibus/multiadapter I2C support. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * Version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #include <common.h> 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 #include <asm/io.h> 26 #include <asm/fsl_i2c.h> /* HW definitions */ 27 28 /* The maximum number of microseconds we will wait until another master has 29 * released the bus. If not defined in the board header file, then use a 30 * generic value. 31 */ 32 #ifndef CONFIG_I2C_MBB_TIMEOUT 33 #define CONFIG_I2C_MBB_TIMEOUT 100000 34 #endif 35 36 /* The maximum number of microseconds we will wait for a read or write 37 * operation to complete. If not defined in the board header file, then use a 38 * generic value. 39 */ 40 #ifndef CONFIG_I2C_TIMEOUT 41 #define CONFIG_I2C_TIMEOUT 10000 42 #endif 43 44 #define I2C_READ_BIT 1 45 #define I2C_WRITE_BIT 0 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 static const struct fsl_i2c *i2c_dev[2] = { 50 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET), 51 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET 52 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET) 53 #endif 54 }; 55 56 /* I2C speed map for a DFSR value of 1 */ 57 58 /* 59 * Map I2C frequency dividers to FDR and DFSR values 60 * 61 * This structure is used to define the elements of a table that maps I2C 62 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 63 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 64 * Sampling Rate (DFSR) registers. 65 * 66 * The actual table should be defined in the board file, and it must be called 67 * fsl_i2c_speed_map[]. 68 * 69 * The last entry of the table must have a value of {-1, X}, where X is same 70 * FDR/DFSR values as the second-to-last entry. This guarantees that any 71 * search through the array will always find a match. 72 * 73 * The values of the divider must be in increasing numerical order, i.e. 74 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 75 * 76 * For this table, the values are based on a value of 1 for the DFSR 77 * register. See the application note AN2919 "Determining the I2C Frequency 78 * Divider Ratio for SCL" 79 * 80 * ColdFire I2C frequency dividers for FDR values are different from 81 * PowerPC. The protocol to use the I2C module is still the same. 82 * A different table is defined and are based on MCF5xxx user manual. 83 * 84 */ 85 static const struct { 86 unsigned short divider; 87 u8 fdr; 88 } fsl_i2c_speed_map[] = { 89 #ifdef __M68K__ 90 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 91 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 92 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 93 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 94 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 95 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 96 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 97 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 98 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 99 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 100 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 101 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 102 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 103 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 104 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 105 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 106 {-1, 31} 107 #endif 108 }; 109 110 /** 111 * Set the I2C bus speed for a given I2C device 112 * 113 * @param dev: the I2C device 114 * @i2c_clk: I2C bus clock frequency 115 * @speed: the desired speed of the bus 116 * 117 * The I2C device must be stopped before calling this function. 118 * 119 * The return value is the actual bus speed that is set. 120 */ 121 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 122 unsigned int i2c_clk, unsigned int speed) 123 { 124 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 125 126 /* 127 * We want to choose an FDR/DFSR that generates an I2C bus speed that 128 * is equal to or lower than the requested speed. That means that we 129 * want the first divider that is equal to or greater than the 130 * calculated divider. 131 */ 132 #ifdef __PPC__ 133 u8 dfsr, fdr = 0x31; /* Default if no FDR found */ 134 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ 135 unsigned short a, b, ga, gb; 136 unsigned long c_div, est_div; 137 138 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR 139 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; 140 #else 141 /* Condition 1: dfsr <= 50/T */ 142 dfsr = (5 * (i2c_clk / 1000)) / 100000; 143 #endif 144 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR 145 fdr = CONFIG_FSL_I2C_CUSTOM_FDR; 146 speed = i2c_clk / divider; /* Fake something */ 147 #else 148 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk); 149 if (!dfsr) 150 dfsr = 1; 151 152 est_div = ~0; 153 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { 154 for (gb = 0; gb < 8; gb++) { 155 b = 16 << gb; 156 c_div = b * (a + ((3*dfsr)/b)*2); 157 if ((c_div > divider) && (c_div < est_div)) { 158 unsigned short bin_gb, bin_ga; 159 160 est_div = c_div; 161 bin_gb = gb << 2; 162 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); 163 fdr = bin_gb | bin_ga; 164 speed = i2c_clk / est_div; 165 debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, " 166 "a:%d, b:%d, speed:%d\n", 167 fdr, est_div, ga, gb, a, b, speed); 168 /* Condition 2 not accounted for */ 169 debug("Tr <= %d ns\n", 170 (b - 3 * dfsr) * 1000000 / 171 (i2c_clk / 1000)); 172 } 173 } 174 if (a == 20) 175 a += 2; 176 if (a == 24) 177 a += 4; 178 } 179 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); 180 debug("FDR:0x%.2x, speed:%d\n", fdr, speed); 181 #endif 182 writeb(dfsr, &dev->dfsrr); /* set default filter */ 183 writeb(fdr, &dev->fdr); /* set bus speed */ 184 #else 185 unsigned int i; 186 187 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 188 if (fsl_i2c_speed_map[i].divider >= divider) { 189 u8 fdr; 190 191 fdr = fsl_i2c_speed_map[i].fdr; 192 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 193 writeb(fdr, &dev->fdr); /* set bus speed */ 194 195 break; 196 } 197 #endif 198 return speed; 199 } 200 201 static unsigned int get_i2c_clock(int bus) 202 { 203 if (bus) 204 return gd->arch.i2c2_clk; /* I2C2 clock */ 205 else 206 return gd->arch.i2c1_clk; /* I2C1 clock */ 207 } 208 209 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 210 { 211 const struct fsl_i2c *dev; 212 213 #ifdef CONFIG_SYS_I2C_INIT_BOARD 214 /* Call board specific i2c bus reset routine before accessing the 215 * environment, which might be in a chip on that bus. For details 216 * about this problem see doc/I2C_Edge_Conditions. 217 */ 218 i2c_init_board(); 219 #endif 220 dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 221 222 writeb(0, &dev->cr); /* stop I2C controller */ 223 udelay(5); /* let it shutdown in peace */ 224 set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed); 225 writeb(slaveadd << 1, &dev->adr);/* write slave address */ 226 writeb(0x0, &dev->sr); /* clear status register */ 227 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 228 229 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT 230 /* Call board specific i2c bus reset routine AFTER the bus has been 231 * initialized. Use either this callpoint or i2c_init_board; 232 * which is called before i2c_init operations. 233 * For details about this problem see doc/I2C_Edge_Conditions. 234 */ 235 i2c_board_late_init(); 236 #endif 237 } 238 239 static int 240 i2c_wait4bus(struct i2c_adapter *adap) 241 { 242 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 243 unsigned long long timeval = get_ticks(); 244 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); 245 246 while (readb(&dev->sr) & I2C_SR_MBB) { 247 if ((get_ticks() - timeval) > timeout) 248 return -1; 249 } 250 251 return 0; 252 } 253 254 static __inline__ int 255 i2c_wait(struct i2c_adapter *adap, int write) 256 { 257 u32 csr; 258 unsigned long long timeval = get_ticks(); 259 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); 260 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 261 262 do { 263 csr = readb(&dev->sr); 264 if (!(csr & I2C_SR_MIF)) 265 continue; 266 /* Read again to allow register to stabilise */ 267 csr = readb(&dev->sr); 268 269 writeb(0x0, &dev->sr); 270 271 if (csr & I2C_SR_MAL) { 272 debug("i2c_wait: MAL\n"); 273 return -1; 274 } 275 276 if (!(csr & I2C_SR_MCF)) { 277 debug("i2c_wait: unfinished\n"); 278 return -1; 279 } 280 281 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 282 debug("i2c_wait: No RXACK\n"); 283 return -1; 284 } 285 286 return 0; 287 } while ((get_ticks() - timeval) < timeout); 288 289 debug("i2c_wait: timed out\n"); 290 return -1; 291 } 292 293 static __inline__ int 294 i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta) 295 { 296 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 297 298 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 299 | (rsta ? I2C_CR_RSTA : 0), 300 &device->cr); 301 302 writeb((dev << 1) | dir, &device->dr); 303 304 if (i2c_wait(adap, I2C_WRITE_BIT) < 0) 305 return 0; 306 307 return 1; 308 } 309 310 static __inline__ int 311 __i2c_write(struct i2c_adapter *adap, u8 *data, int length) 312 { 313 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 314 int i; 315 316 for (i = 0; i < length; i++) { 317 writeb(data[i], &dev->dr); 318 319 if (i2c_wait(adap, I2C_WRITE_BIT) < 0) 320 break; 321 } 322 323 return i; 324 } 325 326 static __inline__ int 327 __i2c_read(struct i2c_adapter *adap, u8 *data, int length) 328 { 329 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 330 int i; 331 332 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 333 &dev->cr); 334 335 /* dummy read */ 336 readb(&dev->dr); 337 338 for (i = 0; i < length; i++) { 339 if (i2c_wait(adap, I2C_READ_BIT) < 0) 340 break; 341 342 /* Generate ack on last next to last byte */ 343 if (i == length - 2) 344 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 345 &dev->cr); 346 347 /* Do not generate stop on last byte */ 348 if (i == length - 1) 349 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, 350 &dev->cr); 351 352 data[i] = readb(&dev->dr); 353 } 354 355 return i; 356 } 357 358 static int 359 fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data, 360 int length) 361 { 362 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 363 int i = -1; /* signal error */ 364 u8 *a = (u8*)&addr; 365 366 if (i2c_wait4bus(adap) < 0) 367 return -1; 368 369 if ((!length || alen > 0) 370 && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 371 && __i2c_write(adap, &a[4 - alen], alen) == alen) 372 i = 0; /* No error so far */ 373 374 if (length && 375 i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0) 376 i = __i2c_read(adap, data, length); 377 378 writeb(I2C_CR_MEN, &device->cr); 379 380 if (i2c_wait4bus(adap)) /* Wait until STOP */ 381 debug("i2c_read: wait4bus timed out\n"); 382 383 if (i == length) 384 return 0; 385 386 return -1; 387 } 388 389 static int 390 fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen, 391 u8 *data, int length) 392 { 393 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 394 int i = -1; /* signal error */ 395 u8 *a = (u8*)&addr; 396 397 if (i2c_wait4bus(adap) >= 0 && 398 i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 && 399 __i2c_write(adap, &a[4 - alen], alen) == alen) { 400 i = __i2c_write(adap, data, length); 401 } 402 403 writeb(I2C_CR_MEN, &device->cr); 404 if (i2c_wait4bus(adap)) /* Wait until STOP */ 405 debug("i2c_write: wait4bus timed out\n"); 406 407 if (i == length) 408 return 0; 409 410 return -1; 411 } 412 413 static int 414 fsl_i2c_probe(struct i2c_adapter *adap, uchar chip) 415 { 416 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 417 /* For unknow reason the controller will ACK when 418 * probing for a slave with the same address, so skip 419 * it. 420 */ 421 if (chip == (readb(&dev->adr) >> 1)) 422 return -1; 423 424 return fsl_i2c_read(adap, chip, 0, 0, NULL, 0); 425 } 426 427 static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap, 428 unsigned int speed) 429 { 430 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr]; 431 432 writeb(0, &dev->cr); /* stop controller */ 433 set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed); 434 writeb(I2C_CR_MEN, &dev->cr); /* start controller */ 435 436 return 0; 437 } 438 439 /* 440 * Register fsl i2c adapters 441 */ 442 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, 443 fsl_i2c_write, fsl_i2c_set_bus_speed, 444 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE, 445 0) 446 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET 447 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read, 448 fsl_i2c_write, fsl_i2c_set_bus_speed, 449 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, 450 1) 451 #endif 452