1 /* 2 * Copyright (c) 2016, Google Inc 3 * 4 * (C) Copyright 2002 5 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <i2c.h> 13 #include <asm/arch/clk.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/pinmux.h> 16 #include "s3c24x0_i2c.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* HSI2C-specific register description */ 21 22 /* I2C_CTL Register bits */ 23 #define HSI2C_FUNC_MODE_I2C (1u << 0) 24 #define HSI2C_MASTER (1u << 3) 25 #define HSI2C_RXCHON (1u << 6) /* Write/Send */ 26 #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ 27 #define HSI2C_SW_RST (1u << 31) 28 29 /* I2C_FIFO_CTL Register bits */ 30 #define HSI2C_RXFIFO_EN (1u << 0) 31 #define HSI2C_TXFIFO_EN (1u << 1) 32 #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) 33 #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) 34 35 /* I2C_TRAILING_CTL Register bits */ 36 #define HSI2C_TRAILING_COUNT (0xff) 37 38 /* I2C_INT_EN Register bits */ 39 #define HSI2C_TX_UNDERRUN_EN (1u << 2) 40 #define HSI2C_TX_OVERRUN_EN (1u << 3) 41 #define HSI2C_RX_UNDERRUN_EN (1u << 4) 42 #define HSI2C_RX_OVERRUN_EN (1u << 5) 43 #define HSI2C_INT_TRAILING_EN (1u << 6) 44 #define HSI2C_INT_I2C_EN (1u << 9) 45 46 #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ 47 HSI2C_TX_OVERRUN_EN |\ 48 HSI2C_RX_UNDERRUN_EN |\ 49 HSI2C_RX_OVERRUN_EN |\ 50 HSI2C_INT_TRAILING_EN) 51 52 /* I2C_CONF Register bits */ 53 #define HSI2C_AUTO_MODE (1u << 31) 54 #define HSI2C_10BIT_ADDR_MODE (1u << 30) 55 #define HSI2C_HS_MODE (1u << 29) 56 57 /* I2C_AUTO_CONF Register bits */ 58 #define HSI2C_READ_WRITE (1u << 16) 59 #define HSI2C_STOP_AFTER_TRANS (1u << 17) 60 #define HSI2C_MASTER_RUN (1u << 31) 61 62 /* I2C_TIMEOUT Register bits */ 63 #define HSI2C_TIMEOUT_EN (1u << 31) 64 65 /* I2C_TRANS_STATUS register bits */ 66 #define HSI2C_MASTER_BUSY (1u << 17) 67 #define HSI2C_SLAVE_BUSY (1u << 16) 68 #define HSI2C_TIMEOUT_AUTO (1u << 4) 69 #define HSI2C_NO_DEV (1u << 3) 70 #define HSI2C_NO_DEV_ACK (1u << 2) 71 #define HSI2C_TRANS_ABORT (1u << 1) 72 #define HSI2C_TRANS_SUCCESS (1u << 0) 73 #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ 74 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ 75 HSI2C_TRANS_ABORT) 76 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) 77 78 79 /* I2C_FIFO_STAT Register bits */ 80 #define HSI2C_RX_FIFO_EMPTY (1u << 24) 81 #define HSI2C_RX_FIFO_FULL (1u << 23) 82 #define HSI2C_TX_FIFO_EMPTY (1u << 8) 83 #define HSI2C_TX_FIFO_FULL (1u << 7) 84 #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) 85 #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) 86 87 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 88 89 #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */ 90 91 /* 92 * Wait for transfer completion. 93 * 94 * This function reads the interrupt status register waiting for the INT_I2C 95 * bit to be set, which indicates copletion of a transaction. 96 * 97 * @param i2c: pointer to the appropriate register bank 98 * 99 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case 100 * the status bits do not get set in time, or an approrpiate error 101 * value in case of transfer errors. 102 */ 103 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) 104 { 105 int i = HSI2C_TIMEOUT_US; 106 107 while (i-- > 0) { 108 u32 int_status = readl(&i2c->usi_int_stat); 109 110 if (int_status & HSI2C_INT_I2C_EN) { 111 u32 trans_status = readl(&i2c->usi_trans_status); 112 113 /* Deassert pending interrupt. */ 114 writel(int_status, &i2c->usi_int_stat); 115 116 if (trans_status & HSI2C_NO_DEV_ACK) { 117 debug("%s: no ACK from device\n", __func__); 118 return I2C_NACK; 119 } 120 if (trans_status & HSI2C_NO_DEV) { 121 debug("%s: no device\n", __func__); 122 return I2C_NOK; 123 } 124 if (trans_status & HSI2C_TRANS_ABORT) { 125 debug("%s: arbitration lost\n", __func__); 126 return I2C_NOK_LA; 127 } 128 if (trans_status & HSI2C_TIMEOUT_AUTO) { 129 debug("%s: device timed out\n", __func__); 130 return I2C_NOK_TOUT; 131 } 132 return I2C_OK; 133 } 134 udelay(1); 135 } 136 debug("%s: transaction timeout!\n", __func__); 137 return I2C_NOK_TOUT; 138 } 139 140 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) 141 { 142 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 143 ulong clkin; 144 unsigned int op_clk = i2c_bus->clock_frequency; 145 unsigned int i = 0, utemp0 = 0, utemp1 = 0; 146 unsigned int t_ftl_cycle; 147 148 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 149 clkin = get_i2c_clk(); 150 #else 151 clkin = get_PCLK(); 152 #endif 153 /* FPCLK / FI2C = 154 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 155 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 156 * uTemp1 = (TSCLK_L + TSCLK_H + 2) 157 * uTemp2 = TSCLK_L + TSCLK_H 158 */ 159 t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; 160 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 161 162 /* CLK_DIV max is 256 */ 163 for (i = 0; i < 256; i++) { 164 utemp1 = utemp0 / (i + 1); 165 if ((utemp1 < 512) && (utemp1 > 4)) { 166 i2c_bus->clk_cycle = utemp1 - 2; 167 i2c_bus->clk_div = i; 168 return 0; 169 } 170 } 171 return -EINVAL; 172 } 173 174 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) 175 { 176 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 177 unsigned int t_sr_release; 178 unsigned int n_clkdiv; 179 unsigned int t_start_su, t_start_hd; 180 unsigned int t_stop_su; 181 unsigned int t_data_su, t_data_hd; 182 unsigned int t_scl_l, t_scl_h; 183 u32 i2c_timing_s1; 184 u32 i2c_timing_s2; 185 u32 i2c_timing_s3; 186 u32 i2c_timing_sla; 187 188 n_clkdiv = i2c_bus->clk_div; 189 t_scl_l = i2c_bus->clk_cycle / 2; 190 t_scl_h = i2c_bus->clk_cycle / 2; 191 t_start_su = t_scl_l; 192 t_start_hd = t_scl_l; 193 t_stop_su = t_scl_l; 194 t_data_su = t_scl_l / 2; 195 t_data_hd = t_scl_l / 2; 196 t_sr_release = i2c_bus->clk_cycle; 197 198 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 199 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 200 i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; 201 i2c_timing_sla = t_data_hd << 0; 202 203 writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); 204 205 /* Clear to enable Timeout */ 206 clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); 207 208 /* set AUTO mode */ 209 writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); 210 211 /* Enable completion conditions' reporting. */ 212 writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); 213 214 /* Enable FIFOs */ 215 writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); 216 217 /* Currently operating in Fast speed mode. */ 218 writel(i2c_timing_s1, &hsregs->usi_timing_fs1); 219 writel(i2c_timing_s2, &hsregs->usi_timing_fs2); 220 writel(i2c_timing_s3, &hsregs->usi_timing_fs3); 221 writel(i2c_timing_sla, &hsregs->usi_timing_sla); 222 } 223 224 /* SW reset for the high speed bus */ 225 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) 226 { 227 struct exynos5_hsi2c *i2c = i2c_bus->hsregs; 228 u32 i2c_ctl; 229 230 /* Set and clear the bit for reset */ 231 i2c_ctl = readl(&i2c->usi_ctl); 232 i2c_ctl |= HSI2C_SW_RST; 233 writel(i2c_ctl, &i2c->usi_ctl); 234 235 i2c_ctl = readl(&i2c->usi_ctl); 236 i2c_ctl &= ~HSI2C_SW_RST; 237 writel(i2c_ctl, &i2c->usi_ctl); 238 239 /* Initialize the configure registers */ 240 hsi2c_ch_init(i2c_bus); 241 } 242 243 /* 244 * Poll the appropriate bit of the fifo status register until the interface is 245 * ready to process the next byte or timeout expires. 246 * 247 * In addition to the FIFO status register this function also polls the 248 * interrupt status register to be able to detect unexpected transaction 249 * completion. 250 * 251 * When FIFO is ready to process the next byte, this function returns I2C_OK. 252 * If in course of polling the INT_I2C assertion is detected, the function 253 * returns I2C_NOK. If timeout happens before any of the above conditions is 254 * met - the function returns I2C_NOK_TOUT; 255 256 * @param i2c: pointer to the appropriate i2c register bank. 257 * @param rx_transfer: set to True if the receive transaction is in progress. 258 * @return: as described above. 259 */ 260 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) 261 { 262 u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; 263 int i = HSI2C_TIMEOUT_US; 264 265 while (readl(&i2c->usi_fifo_stat) & fifo_bit) { 266 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { 267 /* 268 * There is a chance that assertion of 269 * HSI2C_INT_I2C_EN and deassertion of 270 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's 271 * give FIFO status priority and check it one more 272 * time before reporting interrupt. The interrupt will 273 * be reported next time this function is called. 274 */ 275 if (rx_transfer && 276 !(readl(&i2c->usi_fifo_stat) & fifo_bit)) 277 break; 278 return I2C_NOK; 279 } 280 if (!i--) { 281 debug("%s: FIFO polling timeout!\n", __func__); 282 return I2C_NOK_TOUT; 283 } 284 udelay(1); 285 } 286 return I2C_OK; 287 } 288 289 /* 290 * Preapre hsi2c transaction, either read or write. 291 * 292 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of 293 * the 5420 UM. 294 * 295 * @param i2c: pointer to the appropriate i2c register bank. 296 * @param chip: slave address on the i2c bus (with read/write bit exlcuded) 297 * @param len: number of bytes expected to be sent or received 298 * @param rx_transfer: set to true for receive transactions 299 * @param: issue_stop: set to true if i2c stop condition should be generated 300 * after this transaction. 301 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, 302 * I2C_OK otherwise. 303 */ 304 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, 305 u8 chip, 306 u16 len, 307 bool rx_transfer, 308 bool issue_stop) 309 { 310 u32 conf; 311 312 conf = len | HSI2C_MASTER_RUN; 313 314 if (issue_stop) 315 conf |= HSI2C_STOP_AFTER_TRANS; 316 317 /* Clear to enable Timeout */ 318 writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); 319 320 /* Set slave address */ 321 writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); 322 323 if (rx_transfer) { 324 /* i2c master, read transaction */ 325 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 326 &i2c->usi_ctl); 327 328 /* read up to len bytes, stop after transaction is finished */ 329 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); 330 } else { 331 /* i2c master, write transaction */ 332 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 333 &i2c->usi_ctl); 334 335 /* write up to len bytes, stop after transaction is finished */ 336 writel(conf, &i2c->usi_auto_conf); 337 } 338 339 /* Reset all pending interrupt status bits we care about, if any */ 340 writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); 341 342 return I2C_OK; 343 } 344 345 /* 346 * Wait while i2c bus is settling down (mostly stop gets completed). 347 */ 348 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) 349 { 350 int i = HSI2C_TIMEOUT_US; 351 352 while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { 353 if (!i--) { 354 debug("%s: bus busy\n", __func__); 355 return I2C_NOK_TOUT; 356 } 357 udelay(1); 358 } 359 return I2C_OK; 360 } 361 362 static int hsi2c_write(struct exynos5_hsi2c *i2c, 363 unsigned char chip, 364 unsigned char addr[], 365 unsigned char alen, 366 unsigned char data[], 367 unsigned short len, 368 bool issue_stop) 369 { 370 int i, rv = 0; 371 372 if (!(len + alen)) { 373 /* Writes of zero length not supported in auto mode. */ 374 debug("%s: zero length writes not supported\n", __func__); 375 return I2C_NOK; 376 } 377 378 rv = hsi2c_prepare_transaction 379 (i2c, chip, len + alen, false, issue_stop); 380 if (rv != I2C_OK) 381 return rv; 382 383 /* Move address, if any, and the data, if any, into the FIFO. */ 384 for (i = 0; i < alen; i++) { 385 rv = hsi2c_poll_fifo(i2c, false); 386 if (rv != I2C_OK) { 387 debug("%s: address write failed\n", __func__); 388 goto write_error; 389 } 390 writel(addr[i], &i2c->usi_txdata); 391 } 392 393 for (i = 0; i < len; i++) { 394 rv = hsi2c_poll_fifo(i2c, false); 395 if (rv != I2C_OK) { 396 debug("%s: data write failed\n", __func__); 397 goto write_error; 398 } 399 writel(data[i], &i2c->usi_txdata); 400 } 401 402 rv = hsi2c_wait_for_trx(i2c); 403 404 write_error: 405 if (issue_stop) { 406 int tmp_ret = hsi2c_wait_while_busy(i2c); 407 if (rv == I2C_OK) 408 rv = tmp_ret; 409 } 410 411 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 412 return rv; 413 } 414 415 static int hsi2c_read(struct exynos5_hsi2c *i2c, 416 unsigned char chip, 417 unsigned char addr[], 418 unsigned char alen, 419 unsigned char data[], 420 unsigned short len) 421 { 422 int i, rv, tmp_ret; 423 bool drop_data = false; 424 425 if (!len) { 426 /* Reads of zero length not supported in auto mode. */ 427 debug("%s: zero length read adjusted\n", __func__); 428 drop_data = true; 429 len = 1; 430 } 431 432 if (alen) { 433 /* Internal register adress needs to be written first. */ 434 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); 435 if (rv != I2C_OK) 436 return rv; 437 } 438 439 rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); 440 441 if (rv != I2C_OK) 442 return rv; 443 444 for (i = 0; i < len; i++) { 445 rv = hsi2c_poll_fifo(i2c, true); 446 if (rv != I2C_OK) 447 goto read_err; 448 if (drop_data) 449 continue; 450 data[i] = readl(&i2c->usi_rxdata); 451 } 452 453 rv = hsi2c_wait_for_trx(i2c); 454 455 read_err: 456 tmp_ret = hsi2c_wait_while_busy(i2c); 457 if (rv == I2C_OK) 458 rv = tmp_ret; 459 460 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 461 return rv; 462 } 463 464 static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 465 int nmsgs) 466 { 467 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 468 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 469 int ret; 470 471 for (; nmsgs > 0; nmsgs--, msg++) { 472 if (msg->flags & I2C_M_RD) { 473 ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf, 474 msg->len); 475 } else { 476 ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf, 477 msg->len, true); 478 } 479 if (ret) { 480 exynos5_i2c_reset(i2c_bus); 481 return -EREMOTEIO; 482 } 483 } 484 485 return 0; 486 } 487 488 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 489 { 490 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 491 492 i2c_bus->clock_frequency = speed; 493 494 if (hsi2c_get_clk_details(i2c_bus)) 495 return -EFAULT; 496 hsi2c_ch_init(i2c_bus); 497 498 return 0; 499 } 500 501 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) 502 { 503 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 504 uchar buf[1]; 505 int ret; 506 507 buf[0] = 0; 508 509 /* 510 * What is needed is to send the chip address and verify that the 511 * address was <ACK>ed (i.e. there was a chip at that address which 512 * drove the data line low). 513 */ 514 ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1); 515 516 return ret != I2C_OK; 517 } 518 519 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev) 520 { 521 const void *blob = gd->fdt_blob; 522 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 523 int node; 524 525 node = dev->of_offset; 526 527 i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev); 528 529 i2c_bus->id = pinmux_decode_periph_id(blob, node); 530 531 i2c_bus->clock_frequency = fdtdec_get_int(blob, node, 532 "clock-frequency", 100000); 533 i2c_bus->node = node; 534 i2c_bus->bus_num = dev->seq; 535 536 exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE); 537 538 i2c_bus->active = true; 539 540 return 0; 541 } 542 543 static const struct dm_i2c_ops exynos_hs_i2c_ops = { 544 .xfer = exynos_hs_i2c_xfer, 545 .probe_chip = s3c24x0_i2c_probe, 546 .set_bus_speed = s3c24x0_i2c_set_bus_speed, 547 }; 548 549 static const struct udevice_id exynos_hs_i2c_ids[] = { 550 { .compatible = "samsung,exynos5-hsi2c" }, 551 { } 552 }; 553 554 U_BOOT_DRIVER(hs_i2c) = { 555 .name = "i2c_s3c_hs", 556 .id = UCLASS_I2C, 557 .of_match = exynos_hs_i2c_ids, 558 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, 559 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), 560 .ops = &exynos_hs_i2c_ops, 561 }; 562