1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 237b8eb37SSimon Glass /* 337b8eb37SSimon Glass * Copyright (c) 2016, Google Inc 437b8eb37SSimon Glass * 537b8eb37SSimon Glass * (C) Copyright 2002 637b8eb37SSimon Glass * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 737b8eb37SSimon Glass */ 837b8eb37SSimon Glass 937b8eb37SSimon Glass #include <common.h> 1037b8eb37SSimon Glass #include <dm.h> 1137b8eb37SSimon Glass #include <i2c.h> 1237b8eb37SSimon Glass #include <asm/arch/clk.h> 1337b8eb37SSimon Glass #include <asm/arch/cpu.h> 1437b8eb37SSimon Glass #include <asm/arch/pinmux.h> 1537b8eb37SSimon Glass #include "s3c24x0_i2c.h" 1637b8eb37SSimon Glass 1737b8eb37SSimon Glass DECLARE_GLOBAL_DATA_PTR; 1837b8eb37SSimon Glass 1937b8eb37SSimon Glass /* HSI2C-specific register description */ 2037b8eb37SSimon Glass 2137b8eb37SSimon Glass /* I2C_CTL Register bits */ 2237b8eb37SSimon Glass #define HSI2C_FUNC_MODE_I2C (1u << 0) 2337b8eb37SSimon Glass #define HSI2C_MASTER (1u << 3) 2437b8eb37SSimon Glass #define HSI2C_RXCHON (1u << 6) /* Write/Send */ 2537b8eb37SSimon Glass #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ 2637b8eb37SSimon Glass #define HSI2C_SW_RST (1u << 31) 2737b8eb37SSimon Glass 2837b8eb37SSimon Glass /* I2C_FIFO_CTL Register bits */ 2937b8eb37SSimon Glass #define HSI2C_RXFIFO_EN (1u << 0) 3037b8eb37SSimon Glass #define HSI2C_TXFIFO_EN (1u << 1) 3137b8eb37SSimon Glass #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) 3237b8eb37SSimon Glass #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) 3337b8eb37SSimon Glass 3437b8eb37SSimon Glass /* I2C_TRAILING_CTL Register bits */ 3537b8eb37SSimon Glass #define HSI2C_TRAILING_COUNT (0xff) 3637b8eb37SSimon Glass 3737b8eb37SSimon Glass /* I2C_INT_EN Register bits */ 3837b8eb37SSimon Glass #define HSI2C_TX_UNDERRUN_EN (1u << 2) 3937b8eb37SSimon Glass #define HSI2C_TX_OVERRUN_EN (1u << 3) 4037b8eb37SSimon Glass #define HSI2C_RX_UNDERRUN_EN (1u << 4) 4137b8eb37SSimon Glass #define HSI2C_RX_OVERRUN_EN (1u << 5) 4237b8eb37SSimon Glass #define HSI2C_INT_TRAILING_EN (1u << 6) 4337b8eb37SSimon Glass #define HSI2C_INT_I2C_EN (1u << 9) 4437b8eb37SSimon Glass 4537b8eb37SSimon Glass #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ 4637b8eb37SSimon Glass HSI2C_TX_OVERRUN_EN |\ 4737b8eb37SSimon Glass HSI2C_RX_UNDERRUN_EN |\ 4837b8eb37SSimon Glass HSI2C_RX_OVERRUN_EN |\ 4937b8eb37SSimon Glass HSI2C_INT_TRAILING_EN) 5037b8eb37SSimon Glass 5137b8eb37SSimon Glass /* I2C_CONF Register bits */ 5237b8eb37SSimon Glass #define HSI2C_AUTO_MODE (1u << 31) 5337b8eb37SSimon Glass #define HSI2C_10BIT_ADDR_MODE (1u << 30) 5437b8eb37SSimon Glass #define HSI2C_HS_MODE (1u << 29) 5537b8eb37SSimon Glass 5637b8eb37SSimon Glass /* I2C_AUTO_CONF Register bits */ 5737b8eb37SSimon Glass #define HSI2C_READ_WRITE (1u << 16) 5837b8eb37SSimon Glass #define HSI2C_STOP_AFTER_TRANS (1u << 17) 5937b8eb37SSimon Glass #define HSI2C_MASTER_RUN (1u << 31) 6037b8eb37SSimon Glass 6137b8eb37SSimon Glass /* I2C_TIMEOUT Register bits */ 6237b8eb37SSimon Glass #define HSI2C_TIMEOUT_EN (1u << 31) 6337b8eb37SSimon Glass 6437b8eb37SSimon Glass /* I2C_TRANS_STATUS register bits */ 6537b8eb37SSimon Glass #define HSI2C_MASTER_BUSY (1u << 17) 6637b8eb37SSimon Glass #define HSI2C_SLAVE_BUSY (1u << 16) 6737b8eb37SSimon Glass #define HSI2C_TIMEOUT_AUTO (1u << 4) 6837b8eb37SSimon Glass #define HSI2C_NO_DEV (1u << 3) 6937b8eb37SSimon Glass #define HSI2C_NO_DEV_ACK (1u << 2) 7037b8eb37SSimon Glass #define HSI2C_TRANS_ABORT (1u << 1) 7137b8eb37SSimon Glass #define HSI2C_TRANS_SUCCESS (1u << 0) 7237b8eb37SSimon Glass #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ 7337b8eb37SSimon Glass HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ 7437b8eb37SSimon Glass HSI2C_TRANS_ABORT) 7537b8eb37SSimon Glass #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) 7637b8eb37SSimon Glass 7737b8eb37SSimon Glass 7837b8eb37SSimon Glass /* I2C_FIFO_STAT Register bits */ 7937b8eb37SSimon Glass #define HSI2C_RX_FIFO_EMPTY (1u << 24) 8037b8eb37SSimon Glass #define HSI2C_RX_FIFO_FULL (1u << 23) 8137b8eb37SSimon Glass #define HSI2C_TX_FIFO_EMPTY (1u << 8) 8237b8eb37SSimon Glass #define HSI2C_TX_FIFO_FULL (1u << 7) 8337b8eb37SSimon Glass #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) 8437b8eb37SSimon Glass #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) 8537b8eb37SSimon Glass 8637b8eb37SSimon Glass #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 8737b8eb37SSimon Glass 8837b8eb37SSimon Glass #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */ 8937b8eb37SSimon Glass 9037b8eb37SSimon Glass /* 9137b8eb37SSimon Glass * Wait for transfer completion. 9237b8eb37SSimon Glass * 9337b8eb37SSimon Glass * This function reads the interrupt status register waiting for the INT_I2C 9437b8eb37SSimon Glass * bit to be set, which indicates copletion of a transaction. 9537b8eb37SSimon Glass * 9637b8eb37SSimon Glass * @param i2c: pointer to the appropriate register bank 9737b8eb37SSimon Glass * 9837b8eb37SSimon Glass * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case 9937b8eb37SSimon Glass * the status bits do not get set in time, or an approrpiate error 10037b8eb37SSimon Glass * value in case of transfer errors. 10137b8eb37SSimon Glass */ 10237b8eb37SSimon Glass static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) 10337b8eb37SSimon Glass { 10437b8eb37SSimon Glass int i = HSI2C_TIMEOUT_US; 10537b8eb37SSimon Glass 10637b8eb37SSimon Glass while (i-- > 0) { 10737b8eb37SSimon Glass u32 int_status = readl(&i2c->usi_int_stat); 10837b8eb37SSimon Glass 10937b8eb37SSimon Glass if (int_status & HSI2C_INT_I2C_EN) { 11037b8eb37SSimon Glass u32 trans_status = readl(&i2c->usi_trans_status); 11137b8eb37SSimon Glass 11237b8eb37SSimon Glass /* Deassert pending interrupt. */ 11337b8eb37SSimon Glass writel(int_status, &i2c->usi_int_stat); 11437b8eb37SSimon Glass 11537b8eb37SSimon Glass if (trans_status & HSI2C_NO_DEV_ACK) { 11637b8eb37SSimon Glass debug("%s: no ACK from device\n", __func__); 11737b8eb37SSimon Glass return I2C_NACK; 11837b8eb37SSimon Glass } 11937b8eb37SSimon Glass if (trans_status & HSI2C_NO_DEV) { 12037b8eb37SSimon Glass debug("%s: no device\n", __func__); 12137b8eb37SSimon Glass return I2C_NOK; 12237b8eb37SSimon Glass } 12337b8eb37SSimon Glass if (trans_status & HSI2C_TRANS_ABORT) { 12437b8eb37SSimon Glass debug("%s: arbitration lost\n", __func__); 12537b8eb37SSimon Glass return I2C_NOK_LA; 12637b8eb37SSimon Glass } 12737b8eb37SSimon Glass if (trans_status & HSI2C_TIMEOUT_AUTO) { 12837b8eb37SSimon Glass debug("%s: device timed out\n", __func__); 12937b8eb37SSimon Glass return I2C_NOK_TOUT; 13037b8eb37SSimon Glass } 13137b8eb37SSimon Glass return I2C_OK; 13237b8eb37SSimon Glass } 13337b8eb37SSimon Glass udelay(1); 13437b8eb37SSimon Glass } 13537b8eb37SSimon Glass debug("%s: transaction timeout!\n", __func__); 13637b8eb37SSimon Glass return I2C_NOK_TOUT; 13737b8eb37SSimon Glass } 13837b8eb37SSimon Glass 13937b8eb37SSimon Glass static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) 14037b8eb37SSimon Glass { 14137b8eb37SSimon Glass struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 14237b8eb37SSimon Glass ulong clkin; 14337b8eb37SSimon Glass unsigned int op_clk = i2c_bus->clock_frequency; 14437b8eb37SSimon Glass unsigned int i = 0, utemp0 = 0, utemp1 = 0; 14537b8eb37SSimon Glass unsigned int t_ftl_cycle; 14637b8eb37SSimon Glass 14737b8eb37SSimon Glass #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 14837b8eb37SSimon Glass clkin = get_i2c_clk(); 14937b8eb37SSimon Glass #else 15037b8eb37SSimon Glass clkin = get_PCLK(); 15137b8eb37SSimon Glass #endif 15237b8eb37SSimon Glass /* FPCLK / FI2C = 15337b8eb37SSimon Glass * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 15437b8eb37SSimon Glass * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 15537b8eb37SSimon Glass * uTemp1 = (TSCLK_L + TSCLK_H + 2) 15637b8eb37SSimon Glass * uTemp2 = TSCLK_L + TSCLK_H 15737b8eb37SSimon Glass */ 15837b8eb37SSimon Glass t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; 15937b8eb37SSimon Glass utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 16037b8eb37SSimon Glass 16137b8eb37SSimon Glass /* CLK_DIV max is 256 */ 16237b8eb37SSimon Glass for (i = 0; i < 256; i++) { 16337b8eb37SSimon Glass utemp1 = utemp0 / (i + 1); 16437b8eb37SSimon Glass if ((utemp1 < 512) && (utemp1 > 4)) { 16537b8eb37SSimon Glass i2c_bus->clk_cycle = utemp1 - 2; 16637b8eb37SSimon Glass i2c_bus->clk_div = i; 16737b8eb37SSimon Glass return 0; 16837b8eb37SSimon Glass } 16937b8eb37SSimon Glass } 17037b8eb37SSimon Glass return -EINVAL; 17137b8eb37SSimon Glass } 17237b8eb37SSimon Glass 17337b8eb37SSimon Glass static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) 17437b8eb37SSimon Glass { 17537b8eb37SSimon Glass struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 17637b8eb37SSimon Glass unsigned int t_sr_release; 17737b8eb37SSimon Glass unsigned int n_clkdiv; 17837b8eb37SSimon Glass unsigned int t_start_su, t_start_hd; 17937b8eb37SSimon Glass unsigned int t_stop_su; 18037b8eb37SSimon Glass unsigned int t_data_su, t_data_hd; 18137b8eb37SSimon Glass unsigned int t_scl_l, t_scl_h; 18237b8eb37SSimon Glass u32 i2c_timing_s1; 18337b8eb37SSimon Glass u32 i2c_timing_s2; 18437b8eb37SSimon Glass u32 i2c_timing_s3; 18537b8eb37SSimon Glass u32 i2c_timing_sla; 18637b8eb37SSimon Glass 18737b8eb37SSimon Glass n_clkdiv = i2c_bus->clk_div; 18837b8eb37SSimon Glass t_scl_l = i2c_bus->clk_cycle / 2; 18937b8eb37SSimon Glass t_scl_h = i2c_bus->clk_cycle / 2; 19037b8eb37SSimon Glass t_start_su = t_scl_l; 19137b8eb37SSimon Glass t_start_hd = t_scl_l; 19237b8eb37SSimon Glass t_stop_su = t_scl_l; 19337b8eb37SSimon Glass t_data_su = t_scl_l / 2; 19437b8eb37SSimon Glass t_data_hd = t_scl_l / 2; 19537b8eb37SSimon Glass t_sr_release = i2c_bus->clk_cycle; 19637b8eb37SSimon Glass 19737b8eb37SSimon Glass i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 19837b8eb37SSimon Glass i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 19937b8eb37SSimon Glass i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; 20037b8eb37SSimon Glass i2c_timing_sla = t_data_hd << 0; 20137b8eb37SSimon Glass 20237b8eb37SSimon Glass writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); 20337b8eb37SSimon Glass 20437b8eb37SSimon Glass /* Clear to enable Timeout */ 20537b8eb37SSimon Glass clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); 20637b8eb37SSimon Glass 20737b8eb37SSimon Glass /* set AUTO mode */ 20837b8eb37SSimon Glass writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); 20937b8eb37SSimon Glass 21037b8eb37SSimon Glass /* Enable completion conditions' reporting. */ 21137b8eb37SSimon Glass writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); 21237b8eb37SSimon Glass 21337b8eb37SSimon Glass /* Enable FIFOs */ 21437b8eb37SSimon Glass writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); 21537b8eb37SSimon Glass 21637b8eb37SSimon Glass /* Currently operating in Fast speed mode. */ 21737b8eb37SSimon Glass writel(i2c_timing_s1, &hsregs->usi_timing_fs1); 21837b8eb37SSimon Glass writel(i2c_timing_s2, &hsregs->usi_timing_fs2); 21937b8eb37SSimon Glass writel(i2c_timing_s3, &hsregs->usi_timing_fs3); 22037b8eb37SSimon Glass writel(i2c_timing_sla, &hsregs->usi_timing_sla); 22137b8eb37SSimon Glass } 22237b8eb37SSimon Glass 22337b8eb37SSimon Glass /* SW reset for the high speed bus */ 22437b8eb37SSimon Glass static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) 22537b8eb37SSimon Glass { 22637b8eb37SSimon Glass struct exynos5_hsi2c *i2c = i2c_bus->hsregs; 22737b8eb37SSimon Glass u32 i2c_ctl; 22837b8eb37SSimon Glass 22937b8eb37SSimon Glass /* Set and clear the bit for reset */ 23037b8eb37SSimon Glass i2c_ctl = readl(&i2c->usi_ctl); 23137b8eb37SSimon Glass i2c_ctl |= HSI2C_SW_RST; 23237b8eb37SSimon Glass writel(i2c_ctl, &i2c->usi_ctl); 23337b8eb37SSimon Glass 23437b8eb37SSimon Glass i2c_ctl = readl(&i2c->usi_ctl); 23537b8eb37SSimon Glass i2c_ctl &= ~HSI2C_SW_RST; 23637b8eb37SSimon Glass writel(i2c_ctl, &i2c->usi_ctl); 23737b8eb37SSimon Glass 23837b8eb37SSimon Glass /* Initialize the configure registers */ 23937b8eb37SSimon Glass hsi2c_ch_init(i2c_bus); 24037b8eb37SSimon Glass } 24137b8eb37SSimon Glass 24237b8eb37SSimon Glass /* 24337b8eb37SSimon Glass * Poll the appropriate bit of the fifo status register until the interface is 24437b8eb37SSimon Glass * ready to process the next byte or timeout expires. 24537b8eb37SSimon Glass * 24637b8eb37SSimon Glass * In addition to the FIFO status register this function also polls the 24737b8eb37SSimon Glass * interrupt status register to be able to detect unexpected transaction 24837b8eb37SSimon Glass * completion. 24937b8eb37SSimon Glass * 25037b8eb37SSimon Glass * When FIFO is ready to process the next byte, this function returns I2C_OK. 25137b8eb37SSimon Glass * If in course of polling the INT_I2C assertion is detected, the function 25237b8eb37SSimon Glass * returns I2C_NOK. If timeout happens before any of the above conditions is 25337b8eb37SSimon Glass * met - the function returns I2C_NOK_TOUT; 25437b8eb37SSimon Glass 25537b8eb37SSimon Glass * @param i2c: pointer to the appropriate i2c register bank. 25637b8eb37SSimon Glass * @param rx_transfer: set to True if the receive transaction is in progress. 25737b8eb37SSimon Glass * @return: as described above. 25837b8eb37SSimon Glass */ 25937b8eb37SSimon Glass static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) 26037b8eb37SSimon Glass { 26137b8eb37SSimon Glass u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; 26237b8eb37SSimon Glass int i = HSI2C_TIMEOUT_US; 26337b8eb37SSimon Glass 26437b8eb37SSimon Glass while (readl(&i2c->usi_fifo_stat) & fifo_bit) { 26537b8eb37SSimon Glass if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { 26637b8eb37SSimon Glass /* 26737b8eb37SSimon Glass * There is a chance that assertion of 26837b8eb37SSimon Glass * HSI2C_INT_I2C_EN and deassertion of 26937b8eb37SSimon Glass * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's 27037b8eb37SSimon Glass * give FIFO status priority and check it one more 27137b8eb37SSimon Glass * time before reporting interrupt. The interrupt will 27237b8eb37SSimon Glass * be reported next time this function is called. 27337b8eb37SSimon Glass */ 27437b8eb37SSimon Glass if (rx_transfer && 27537b8eb37SSimon Glass !(readl(&i2c->usi_fifo_stat) & fifo_bit)) 27637b8eb37SSimon Glass break; 27737b8eb37SSimon Glass return I2C_NOK; 27837b8eb37SSimon Glass } 27937b8eb37SSimon Glass if (!i--) { 28037b8eb37SSimon Glass debug("%s: FIFO polling timeout!\n", __func__); 28137b8eb37SSimon Glass return I2C_NOK_TOUT; 28237b8eb37SSimon Glass } 28337b8eb37SSimon Glass udelay(1); 28437b8eb37SSimon Glass } 28537b8eb37SSimon Glass return I2C_OK; 28637b8eb37SSimon Glass } 28737b8eb37SSimon Glass 28837b8eb37SSimon Glass /* 28937b8eb37SSimon Glass * Preapre hsi2c transaction, either read or write. 29037b8eb37SSimon Glass * 29137b8eb37SSimon Glass * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of 29237b8eb37SSimon Glass * the 5420 UM. 29337b8eb37SSimon Glass * 29437b8eb37SSimon Glass * @param i2c: pointer to the appropriate i2c register bank. 29537b8eb37SSimon Glass * @param chip: slave address on the i2c bus (with read/write bit exlcuded) 29637b8eb37SSimon Glass * @param len: number of bytes expected to be sent or received 29737b8eb37SSimon Glass * @param rx_transfer: set to true for receive transactions 29837b8eb37SSimon Glass * @param: issue_stop: set to true if i2c stop condition should be generated 29937b8eb37SSimon Glass * after this transaction. 30037b8eb37SSimon Glass * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, 30137b8eb37SSimon Glass * I2C_OK otherwise. 30237b8eb37SSimon Glass */ 30337b8eb37SSimon Glass static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, 30437b8eb37SSimon Glass u8 chip, 30537b8eb37SSimon Glass u16 len, 30637b8eb37SSimon Glass bool rx_transfer, 30737b8eb37SSimon Glass bool issue_stop) 30837b8eb37SSimon Glass { 30937b8eb37SSimon Glass u32 conf; 31037b8eb37SSimon Glass 31137b8eb37SSimon Glass conf = len | HSI2C_MASTER_RUN; 31237b8eb37SSimon Glass 31337b8eb37SSimon Glass if (issue_stop) 31437b8eb37SSimon Glass conf |= HSI2C_STOP_AFTER_TRANS; 31537b8eb37SSimon Glass 31637b8eb37SSimon Glass /* Clear to enable Timeout */ 31737b8eb37SSimon Glass writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); 31837b8eb37SSimon Glass 31937b8eb37SSimon Glass /* Set slave address */ 32037b8eb37SSimon Glass writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); 32137b8eb37SSimon Glass 32237b8eb37SSimon Glass if (rx_transfer) { 32337b8eb37SSimon Glass /* i2c master, read transaction */ 32437b8eb37SSimon Glass writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 32537b8eb37SSimon Glass &i2c->usi_ctl); 32637b8eb37SSimon Glass 32737b8eb37SSimon Glass /* read up to len bytes, stop after transaction is finished */ 32837b8eb37SSimon Glass writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); 32937b8eb37SSimon Glass } else { 33037b8eb37SSimon Glass /* i2c master, write transaction */ 33137b8eb37SSimon Glass writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 33237b8eb37SSimon Glass &i2c->usi_ctl); 33337b8eb37SSimon Glass 33437b8eb37SSimon Glass /* write up to len bytes, stop after transaction is finished */ 33537b8eb37SSimon Glass writel(conf, &i2c->usi_auto_conf); 33637b8eb37SSimon Glass } 33737b8eb37SSimon Glass 33837b8eb37SSimon Glass /* Reset all pending interrupt status bits we care about, if any */ 33937b8eb37SSimon Glass writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); 34037b8eb37SSimon Glass 34137b8eb37SSimon Glass return I2C_OK; 34237b8eb37SSimon Glass } 34337b8eb37SSimon Glass 34437b8eb37SSimon Glass /* 34537b8eb37SSimon Glass * Wait while i2c bus is settling down (mostly stop gets completed). 34637b8eb37SSimon Glass */ 34737b8eb37SSimon Glass static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) 34837b8eb37SSimon Glass { 34937b8eb37SSimon Glass int i = HSI2C_TIMEOUT_US; 35037b8eb37SSimon Glass 35137b8eb37SSimon Glass while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { 35237b8eb37SSimon Glass if (!i--) { 35337b8eb37SSimon Glass debug("%s: bus busy\n", __func__); 35437b8eb37SSimon Glass return I2C_NOK_TOUT; 35537b8eb37SSimon Glass } 35637b8eb37SSimon Glass udelay(1); 35737b8eb37SSimon Glass } 35837b8eb37SSimon Glass return I2C_OK; 35937b8eb37SSimon Glass } 36037b8eb37SSimon Glass 36137b8eb37SSimon Glass static int hsi2c_write(struct exynos5_hsi2c *i2c, 36237b8eb37SSimon Glass unsigned char chip, 36337b8eb37SSimon Glass unsigned char addr[], 36437b8eb37SSimon Glass unsigned char alen, 36537b8eb37SSimon Glass unsigned char data[], 36637b8eb37SSimon Glass unsigned short len, 36737b8eb37SSimon Glass bool issue_stop) 36837b8eb37SSimon Glass { 36937b8eb37SSimon Glass int i, rv = 0; 37037b8eb37SSimon Glass 37137b8eb37SSimon Glass if (!(len + alen)) { 37237b8eb37SSimon Glass /* Writes of zero length not supported in auto mode. */ 37337b8eb37SSimon Glass debug("%s: zero length writes not supported\n", __func__); 37437b8eb37SSimon Glass return I2C_NOK; 37537b8eb37SSimon Glass } 37637b8eb37SSimon Glass 37737b8eb37SSimon Glass rv = hsi2c_prepare_transaction 37837b8eb37SSimon Glass (i2c, chip, len + alen, false, issue_stop); 37937b8eb37SSimon Glass if (rv != I2C_OK) 38037b8eb37SSimon Glass return rv; 38137b8eb37SSimon Glass 38237b8eb37SSimon Glass /* Move address, if any, and the data, if any, into the FIFO. */ 38337b8eb37SSimon Glass for (i = 0; i < alen; i++) { 38437b8eb37SSimon Glass rv = hsi2c_poll_fifo(i2c, false); 38537b8eb37SSimon Glass if (rv != I2C_OK) { 38637b8eb37SSimon Glass debug("%s: address write failed\n", __func__); 38737b8eb37SSimon Glass goto write_error; 38837b8eb37SSimon Glass } 38937b8eb37SSimon Glass writel(addr[i], &i2c->usi_txdata); 39037b8eb37SSimon Glass } 39137b8eb37SSimon Glass 39237b8eb37SSimon Glass for (i = 0; i < len; i++) { 39337b8eb37SSimon Glass rv = hsi2c_poll_fifo(i2c, false); 39437b8eb37SSimon Glass if (rv != I2C_OK) { 39537b8eb37SSimon Glass debug("%s: data write failed\n", __func__); 39637b8eb37SSimon Glass goto write_error; 39737b8eb37SSimon Glass } 39837b8eb37SSimon Glass writel(data[i], &i2c->usi_txdata); 39937b8eb37SSimon Glass } 40037b8eb37SSimon Glass 40137b8eb37SSimon Glass rv = hsi2c_wait_for_trx(i2c); 40237b8eb37SSimon Glass 40337b8eb37SSimon Glass write_error: 40437b8eb37SSimon Glass if (issue_stop) { 40537b8eb37SSimon Glass int tmp_ret = hsi2c_wait_while_busy(i2c); 40637b8eb37SSimon Glass if (rv == I2C_OK) 40737b8eb37SSimon Glass rv = tmp_ret; 40837b8eb37SSimon Glass } 40937b8eb37SSimon Glass 41037b8eb37SSimon Glass writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 41137b8eb37SSimon Glass return rv; 41237b8eb37SSimon Glass } 41337b8eb37SSimon Glass 41437b8eb37SSimon Glass static int hsi2c_read(struct exynos5_hsi2c *i2c, 41537b8eb37SSimon Glass unsigned char chip, 41637b8eb37SSimon Glass unsigned char addr[], 41737b8eb37SSimon Glass unsigned char alen, 41837b8eb37SSimon Glass unsigned char data[], 41937b8eb37SSimon Glass unsigned short len) 42037b8eb37SSimon Glass { 42137b8eb37SSimon Glass int i, rv, tmp_ret; 42237b8eb37SSimon Glass bool drop_data = false; 42337b8eb37SSimon Glass 42437b8eb37SSimon Glass if (!len) { 42537b8eb37SSimon Glass /* Reads of zero length not supported in auto mode. */ 42637b8eb37SSimon Glass debug("%s: zero length read adjusted\n", __func__); 42737b8eb37SSimon Glass drop_data = true; 42837b8eb37SSimon Glass len = 1; 42937b8eb37SSimon Glass } 43037b8eb37SSimon Glass 43137b8eb37SSimon Glass if (alen) { 43237b8eb37SSimon Glass /* Internal register adress needs to be written first. */ 43337b8eb37SSimon Glass rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); 43437b8eb37SSimon Glass if (rv != I2C_OK) 43537b8eb37SSimon Glass return rv; 43637b8eb37SSimon Glass } 43737b8eb37SSimon Glass 43837b8eb37SSimon Glass rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); 43937b8eb37SSimon Glass 44037b8eb37SSimon Glass if (rv != I2C_OK) 44137b8eb37SSimon Glass return rv; 44237b8eb37SSimon Glass 44337b8eb37SSimon Glass for (i = 0; i < len; i++) { 44437b8eb37SSimon Glass rv = hsi2c_poll_fifo(i2c, true); 44537b8eb37SSimon Glass if (rv != I2C_OK) 44637b8eb37SSimon Glass goto read_err; 44737b8eb37SSimon Glass if (drop_data) 44837b8eb37SSimon Glass continue; 44937b8eb37SSimon Glass data[i] = readl(&i2c->usi_rxdata); 45037b8eb37SSimon Glass } 45137b8eb37SSimon Glass 45237b8eb37SSimon Glass rv = hsi2c_wait_for_trx(i2c); 45337b8eb37SSimon Glass 45437b8eb37SSimon Glass read_err: 45537b8eb37SSimon Glass tmp_ret = hsi2c_wait_while_busy(i2c); 45637b8eb37SSimon Glass if (rv == I2C_OK) 45737b8eb37SSimon Glass rv = tmp_ret; 45837b8eb37SSimon Glass 45937b8eb37SSimon Glass writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 46037b8eb37SSimon Glass return rv; 46137b8eb37SSimon Glass } 46237b8eb37SSimon Glass 46337b8eb37SSimon Glass static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 46437b8eb37SSimon Glass int nmsgs) 46537b8eb37SSimon Glass { 46637b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 46737b8eb37SSimon Glass struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 46837b8eb37SSimon Glass int ret; 46937b8eb37SSimon Glass 47037b8eb37SSimon Glass for (; nmsgs > 0; nmsgs--, msg++) { 47137b8eb37SSimon Glass if (msg->flags & I2C_M_RD) { 47237b8eb37SSimon Glass ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf, 47337b8eb37SSimon Glass msg->len); 47437b8eb37SSimon Glass } else { 47537b8eb37SSimon Glass ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf, 47637b8eb37SSimon Glass msg->len, true); 47737b8eb37SSimon Glass } 47837b8eb37SSimon Glass if (ret) { 47937b8eb37SSimon Glass exynos5_i2c_reset(i2c_bus); 48037b8eb37SSimon Glass return -EREMOTEIO; 48137b8eb37SSimon Glass } 48237b8eb37SSimon Glass } 48337b8eb37SSimon Glass 48437b8eb37SSimon Glass return 0; 48537b8eb37SSimon Glass } 48637b8eb37SSimon Glass 48737b8eb37SSimon Glass static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 48837b8eb37SSimon Glass { 48937b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 49037b8eb37SSimon Glass 49137b8eb37SSimon Glass i2c_bus->clock_frequency = speed; 49237b8eb37SSimon Glass 49337b8eb37SSimon Glass if (hsi2c_get_clk_details(i2c_bus)) 49437b8eb37SSimon Glass return -EFAULT; 49537b8eb37SSimon Glass hsi2c_ch_init(i2c_bus); 49637b8eb37SSimon Glass 49737b8eb37SSimon Glass return 0; 49837b8eb37SSimon Glass } 49937b8eb37SSimon Glass 50037b8eb37SSimon Glass static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) 50137b8eb37SSimon Glass { 50237b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 50337b8eb37SSimon Glass uchar buf[1]; 50437b8eb37SSimon Glass int ret; 50537b8eb37SSimon Glass 50637b8eb37SSimon Glass buf[0] = 0; 50737b8eb37SSimon Glass 50837b8eb37SSimon Glass /* 50937b8eb37SSimon Glass * What is needed is to send the chip address and verify that the 51037b8eb37SSimon Glass * address was <ACK>ed (i.e. there was a chip at that address which 51137b8eb37SSimon Glass * drove the data line low). 51237b8eb37SSimon Glass */ 51337b8eb37SSimon Glass ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1); 51437b8eb37SSimon Glass 51537b8eb37SSimon Glass return ret != I2C_OK; 51637b8eb37SSimon Glass } 51737b8eb37SSimon Glass 51837b8eb37SSimon Glass static int s3c_i2c_ofdata_to_platdata(struct udevice *dev) 51937b8eb37SSimon Glass { 52037b8eb37SSimon Glass const void *blob = gd->fdt_blob; 52137b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 52237b8eb37SSimon Glass int node; 52337b8eb37SSimon Glass 524e160f7d4SSimon Glass node = dev_of_offset(dev); 52537b8eb37SSimon Glass 526a821c4afSSimon Glass i2c_bus->hsregs = (struct exynos5_hsi2c *)devfdt_get_addr(dev); 52737b8eb37SSimon Glass 52837b8eb37SSimon Glass i2c_bus->id = pinmux_decode_periph_id(blob, node); 52937b8eb37SSimon Glass 53037b8eb37SSimon Glass i2c_bus->clock_frequency = fdtdec_get_int(blob, node, 53137b8eb37SSimon Glass "clock-frequency", 100000); 53237b8eb37SSimon Glass i2c_bus->node = node; 53337b8eb37SSimon Glass i2c_bus->bus_num = dev->seq; 53437b8eb37SSimon Glass 53537b8eb37SSimon Glass exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE); 53637b8eb37SSimon Glass 53737b8eb37SSimon Glass i2c_bus->active = true; 53837b8eb37SSimon Glass 53937b8eb37SSimon Glass return 0; 54037b8eb37SSimon Glass } 54137b8eb37SSimon Glass 54237b8eb37SSimon Glass static const struct dm_i2c_ops exynos_hs_i2c_ops = { 54337b8eb37SSimon Glass .xfer = exynos_hs_i2c_xfer, 54437b8eb37SSimon Glass .probe_chip = s3c24x0_i2c_probe, 54537b8eb37SSimon Glass .set_bus_speed = s3c24x0_i2c_set_bus_speed, 54637b8eb37SSimon Glass }; 54737b8eb37SSimon Glass 54837b8eb37SSimon Glass static const struct udevice_id exynos_hs_i2c_ids[] = { 54937b8eb37SSimon Glass { .compatible = "samsung,exynos5-hsi2c" }, 55037b8eb37SSimon Glass { } 55137b8eb37SSimon Glass }; 55237b8eb37SSimon Glass 55337b8eb37SSimon Glass U_BOOT_DRIVER(hs_i2c) = { 55437b8eb37SSimon Glass .name = "i2c_s3c_hs", 55537b8eb37SSimon Glass .id = UCLASS_I2C, 55637b8eb37SSimon Glass .of_match = exynos_hs_i2c_ids, 55737b8eb37SSimon Glass .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, 55837b8eb37SSimon Glass .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), 55937b8eb37SSimon Glass .ops = &exynos_hs_i2c_ops, 56037b8eb37SSimon Glass }; 561