1*37b8eb37SSimon Glass /* 2*37b8eb37SSimon Glass * Copyright (c) 2016, Google Inc 3*37b8eb37SSimon Glass * 4*37b8eb37SSimon Glass * (C) Copyright 2002 5*37b8eb37SSimon Glass * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 6*37b8eb37SSimon Glass * 7*37b8eb37SSimon Glass * SPDX-License-Identifier: GPL-2.0+ 8*37b8eb37SSimon Glass */ 9*37b8eb37SSimon Glass 10*37b8eb37SSimon Glass #include <common.h> 11*37b8eb37SSimon Glass #include <dm.h> 12*37b8eb37SSimon Glass #include <i2c.h> 13*37b8eb37SSimon Glass #include <asm/arch/clk.h> 14*37b8eb37SSimon Glass #include <asm/arch/cpu.h> 15*37b8eb37SSimon Glass #include <asm/arch/pinmux.h> 16*37b8eb37SSimon Glass #include "s3c24x0_i2c.h" 17*37b8eb37SSimon Glass 18*37b8eb37SSimon Glass DECLARE_GLOBAL_DATA_PTR; 19*37b8eb37SSimon Glass 20*37b8eb37SSimon Glass /* HSI2C-specific register description */ 21*37b8eb37SSimon Glass 22*37b8eb37SSimon Glass /* I2C_CTL Register bits */ 23*37b8eb37SSimon Glass #define HSI2C_FUNC_MODE_I2C (1u << 0) 24*37b8eb37SSimon Glass #define HSI2C_MASTER (1u << 3) 25*37b8eb37SSimon Glass #define HSI2C_RXCHON (1u << 6) /* Write/Send */ 26*37b8eb37SSimon Glass #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ 27*37b8eb37SSimon Glass #define HSI2C_SW_RST (1u << 31) 28*37b8eb37SSimon Glass 29*37b8eb37SSimon Glass /* I2C_FIFO_CTL Register bits */ 30*37b8eb37SSimon Glass #define HSI2C_RXFIFO_EN (1u << 0) 31*37b8eb37SSimon Glass #define HSI2C_TXFIFO_EN (1u << 1) 32*37b8eb37SSimon Glass #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) 33*37b8eb37SSimon Glass #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) 34*37b8eb37SSimon Glass 35*37b8eb37SSimon Glass /* I2C_TRAILING_CTL Register bits */ 36*37b8eb37SSimon Glass #define HSI2C_TRAILING_COUNT (0xff) 37*37b8eb37SSimon Glass 38*37b8eb37SSimon Glass /* I2C_INT_EN Register bits */ 39*37b8eb37SSimon Glass #define HSI2C_TX_UNDERRUN_EN (1u << 2) 40*37b8eb37SSimon Glass #define HSI2C_TX_OVERRUN_EN (1u << 3) 41*37b8eb37SSimon Glass #define HSI2C_RX_UNDERRUN_EN (1u << 4) 42*37b8eb37SSimon Glass #define HSI2C_RX_OVERRUN_EN (1u << 5) 43*37b8eb37SSimon Glass #define HSI2C_INT_TRAILING_EN (1u << 6) 44*37b8eb37SSimon Glass #define HSI2C_INT_I2C_EN (1u << 9) 45*37b8eb37SSimon Glass 46*37b8eb37SSimon Glass #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ 47*37b8eb37SSimon Glass HSI2C_TX_OVERRUN_EN |\ 48*37b8eb37SSimon Glass HSI2C_RX_UNDERRUN_EN |\ 49*37b8eb37SSimon Glass HSI2C_RX_OVERRUN_EN |\ 50*37b8eb37SSimon Glass HSI2C_INT_TRAILING_EN) 51*37b8eb37SSimon Glass 52*37b8eb37SSimon Glass /* I2C_CONF Register bits */ 53*37b8eb37SSimon Glass #define HSI2C_AUTO_MODE (1u << 31) 54*37b8eb37SSimon Glass #define HSI2C_10BIT_ADDR_MODE (1u << 30) 55*37b8eb37SSimon Glass #define HSI2C_HS_MODE (1u << 29) 56*37b8eb37SSimon Glass 57*37b8eb37SSimon Glass /* I2C_AUTO_CONF Register bits */ 58*37b8eb37SSimon Glass #define HSI2C_READ_WRITE (1u << 16) 59*37b8eb37SSimon Glass #define HSI2C_STOP_AFTER_TRANS (1u << 17) 60*37b8eb37SSimon Glass #define HSI2C_MASTER_RUN (1u << 31) 61*37b8eb37SSimon Glass 62*37b8eb37SSimon Glass /* I2C_TIMEOUT Register bits */ 63*37b8eb37SSimon Glass #define HSI2C_TIMEOUT_EN (1u << 31) 64*37b8eb37SSimon Glass 65*37b8eb37SSimon Glass /* I2C_TRANS_STATUS register bits */ 66*37b8eb37SSimon Glass #define HSI2C_MASTER_BUSY (1u << 17) 67*37b8eb37SSimon Glass #define HSI2C_SLAVE_BUSY (1u << 16) 68*37b8eb37SSimon Glass #define HSI2C_TIMEOUT_AUTO (1u << 4) 69*37b8eb37SSimon Glass #define HSI2C_NO_DEV (1u << 3) 70*37b8eb37SSimon Glass #define HSI2C_NO_DEV_ACK (1u << 2) 71*37b8eb37SSimon Glass #define HSI2C_TRANS_ABORT (1u << 1) 72*37b8eb37SSimon Glass #define HSI2C_TRANS_SUCCESS (1u << 0) 73*37b8eb37SSimon Glass #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ 74*37b8eb37SSimon Glass HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ 75*37b8eb37SSimon Glass HSI2C_TRANS_ABORT) 76*37b8eb37SSimon Glass #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) 77*37b8eb37SSimon Glass 78*37b8eb37SSimon Glass 79*37b8eb37SSimon Glass /* I2C_FIFO_STAT Register bits */ 80*37b8eb37SSimon Glass #define HSI2C_RX_FIFO_EMPTY (1u << 24) 81*37b8eb37SSimon Glass #define HSI2C_RX_FIFO_FULL (1u << 23) 82*37b8eb37SSimon Glass #define HSI2C_TX_FIFO_EMPTY (1u << 8) 83*37b8eb37SSimon Glass #define HSI2C_TX_FIFO_FULL (1u << 7) 84*37b8eb37SSimon Glass #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) 85*37b8eb37SSimon Glass #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) 86*37b8eb37SSimon Glass 87*37b8eb37SSimon Glass #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 88*37b8eb37SSimon Glass 89*37b8eb37SSimon Glass #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */ 90*37b8eb37SSimon Glass 91*37b8eb37SSimon Glass /* 92*37b8eb37SSimon Glass * Wait for transfer completion. 93*37b8eb37SSimon Glass * 94*37b8eb37SSimon Glass * This function reads the interrupt status register waiting for the INT_I2C 95*37b8eb37SSimon Glass * bit to be set, which indicates copletion of a transaction. 96*37b8eb37SSimon Glass * 97*37b8eb37SSimon Glass * @param i2c: pointer to the appropriate register bank 98*37b8eb37SSimon Glass * 99*37b8eb37SSimon Glass * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case 100*37b8eb37SSimon Glass * the status bits do not get set in time, or an approrpiate error 101*37b8eb37SSimon Glass * value in case of transfer errors. 102*37b8eb37SSimon Glass */ 103*37b8eb37SSimon Glass static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) 104*37b8eb37SSimon Glass { 105*37b8eb37SSimon Glass int i = HSI2C_TIMEOUT_US; 106*37b8eb37SSimon Glass 107*37b8eb37SSimon Glass while (i-- > 0) { 108*37b8eb37SSimon Glass u32 int_status = readl(&i2c->usi_int_stat); 109*37b8eb37SSimon Glass 110*37b8eb37SSimon Glass if (int_status & HSI2C_INT_I2C_EN) { 111*37b8eb37SSimon Glass u32 trans_status = readl(&i2c->usi_trans_status); 112*37b8eb37SSimon Glass 113*37b8eb37SSimon Glass /* Deassert pending interrupt. */ 114*37b8eb37SSimon Glass writel(int_status, &i2c->usi_int_stat); 115*37b8eb37SSimon Glass 116*37b8eb37SSimon Glass if (trans_status & HSI2C_NO_DEV_ACK) { 117*37b8eb37SSimon Glass debug("%s: no ACK from device\n", __func__); 118*37b8eb37SSimon Glass return I2C_NACK; 119*37b8eb37SSimon Glass } 120*37b8eb37SSimon Glass if (trans_status & HSI2C_NO_DEV) { 121*37b8eb37SSimon Glass debug("%s: no device\n", __func__); 122*37b8eb37SSimon Glass return I2C_NOK; 123*37b8eb37SSimon Glass } 124*37b8eb37SSimon Glass if (trans_status & HSI2C_TRANS_ABORT) { 125*37b8eb37SSimon Glass debug("%s: arbitration lost\n", __func__); 126*37b8eb37SSimon Glass return I2C_NOK_LA; 127*37b8eb37SSimon Glass } 128*37b8eb37SSimon Glass if (trans_status & HSI2C_TIMEOUT_AUTO) { 129*37b8eb37SSimon Glass debug("%s: device timed out\n", __func__); 130*37b8eb37SSimon Glass return I2C_NOK_TOUT; 131*37b8eb37SSimon Glass } 132*37b8eb37SSimon Glass return I2C_OK; 133*37b8eb37SSimon Glass } 134*37b8eb37SSimon Glass udelay(1); 135*37b8eb37SSimon Glass } 136*37b8eb37SSimon Glass debug("%s: transaction timeout!\n", __func__); 137*37b8eb37SSimon Glass return I2C_NOK_TOUT; 138*37b8eb37SSimon Glass } 139*37b8eb37SSimon Glass 140*37b8eb37SSimon Glass static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) 141*37b8eb37SSimon Glass { 142*37b8eb37SSimon Glass struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 143*37b8eb37SSimon Glass ulong clkin; 144*37b8eb37SSimon Glass unsigned int op_clk = i2c_bus->clock_frequency; 145*37b8eb37SSimon Glass unsigned int i = 0, utemp0 = 0, utemp1 = 0; 146*37b8eb37SSimon Glass unsigned int t_ftl_cycle; 147*37b8eb37SSimon Glass 148*37b8eb37SSimon Glass #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 149*37b8eb37SSimon Glass clkin = get_i2c_clk(); 150*37b8eb37SSimon Glass #else 151*37b8eb37SSimon Glass clkin = get_PCLK(); 152*37b8eb37SSimon Glass #endif 153*37b8eb37SSimon Glass /* FPCLK / FI2C = 154*37b8eb37SSimon Glass * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 155*37b8eb37SSimon Glass * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 156*37b8eb37SSimon Glass * uTemp1 = (TSCLK_L + TSCLK_H + 2) 157*37b8eb37SSimon Glass * uTemp2 = TSCLK_L + TSCLK_H 158*37b8eb37SSimon Glass */ 159*37b8eb37SSimon Glass t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; 160*37b8eb37SSimon Glass utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 161*37b8eb37SSimon Glass 162*37b8eb37SSimon Glass /* CLK_DIV max is 256 */ 163*37b8eb37SSimon Glass for (i = 0; i < 256; i++) { 164*37b8eb37SSimon Glass utemp1 = utemp0 / (i + 1); 165*37b8eb37SSimon Glass if ((utemp1 < 512) && (utemp1 > 4)) { 166*37b8eb37SSimon Glass i2c_bus->clk_cycle = utemp1 - 2; 167*37b8eb37SSimon Glass i2c_bus->clk_div = i; 168*37b8eb37SSimon Glass return 0; 169*37b8eb37SSimon Glass } 170*37b8eb37SSimon Glass } 171*37b8eb37SSimon Glass return -EINVAL; 172*37b8eb37SSimon Glass } 173*37b8eb37SSimon Glass 174*37b8eb37SSimon Glass static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) 175*37b8eb37SSimon Glass { 176*37b8eb37SSimon Glass struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 177*37b8eb37SSimon Glass unsigned int t_sr_release; 178*37b8eb37SSimon Glass unsigned int n_clkdiv; 179*37b8eb37SSimon Glass unsigned int t_start_su, t_start_hd; 180*37b8eb37SSimon Glass unsigned int t_stop_su; 181*37b8eb37SSimon Glass unsigned int t_data_su, t_data_hd; 182*37b8eb37SSimon Glass unsigned int t_scl_l, t_scl_h; 183*37b8eb37SSimon Glass u32 i2c_timing_s1; 184*37b8eb37SSimon Glass u32 i2c_timing_s2; 185*37b8eb37SSimon Glass u32 i2c_timing_s3; 186*37b8eb37SSimon Glass u32 i2c_timing_sla; 187*37b8eb37SSimon Glass 188*37b8eb37SSimon Glass n_clkdiv = i2c_bus->clk_div; 189*37b8eb37SSimon Glass t_scl_l = i2c_bus->clk_cycle / 2; 190*37b8eb37SSimon Glass t_scl_h = i2c_bus->clk_cycle / 2; 191*37b8eb37SSimon Glass t_start_su = t_scl_l; 192*37b8eb37SSimon Glass t_start_hd = t_scl_l; 193*37b8eb37SSimon Glass t_stop_su = t_scl_l; 194*37b8eb37SSimon Glass t_data_su = t_scl_l / 2; 195*37b8eb37SSimon Glass t_data_hd = t_scl_l / 2; 196*37b8eb37SSimon Glass t_sr_release = i2c_bus->clk_cycle; 197*37b8eb37SSimon Glass 198*37b8eb37SSimon Glass i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 199*37b8eb37SSimon Glass i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 200*37b8eb37SSimon Glass i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; 201*37b8eb37SSimon Glass i2c_timing_sla = t_data_hd << 0; 202*37b8eb37SSimon Glass 203*37b8eb37SSimon Glass writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); 204*37b8eb37SSimon Glass 205*37b8eb37SSimon Glass /* Clear to enable Timeout */ 206*37b8eb37SSimon Glass clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); 207*37b8eb37SSimon Glass 208*37b8eb37SSimon Glass /* set AUTO mode */ 209*37b8eb37SSimon Glass writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); 210*37b8eb37SSimon Glass 211*37b8eb37SSimon Glass /* Enable completion conditions' reporting. */ 212*37b8eb37SSimon Glass writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); 213*37b8eb37SSimon Glass 214*37b8eb37SSimon Glass /* Enable FIFOs */ 215*37b8eb37SSimon Glass writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); 216*37b8eb37SSimon Glass 217*37b8eb37SSimon Glass /* Currently operating in Fast speed mode. */ 218*37b8eb37SSimon Glass writel(i2c_timing_s1, &hsregs->usi_timing_fs1); 219*37b8eb37SSimon Glass writel(i2c_timing_s2, &hsregs->usi_timing_fs2); 220*37b8eb37SSimon Glass writel(i2c_timing_s3, &hsregs->usi_timing_fs3); 221*37b8eb37SSimon Glass writel(i2c_timing_sla, &hsregs->usi_timing_sla); 222*37b8eb37SSimon Glass } 223*37b8eb37SSimon Glass 224*37b8eb37SSimon Glass /* SW reset for the high speed bus */ 225*37b8eb37SSimon Glass static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) 226*37b8eb37SSimon Glass { 227*37b8eb37SSimon Glass struct exynos5_hsi2c *i2c = i2c_bus->hsregs; 228*37b8eb37SSimon Glass u32 i2c_ctl; 229*37b8eb37SSimon Glass 230*37b8eb37SSimon Glass /* Set and clear the bit for reset */ 231*37b8eb37SSimon Glass i2c_ctl = readl(&i2c->usi_ctl); 232*37b8eb37SSimon Glass i2c_ctl |= HSI2C_SW_RST; 233*37b8eb37SSimon Glass writel(i2c_ctl, &i2c->usi_ctl); 234*37b8eb37SSimon Glass 235*37b8eb37SSimon Glass i2c_ctl = readl(&i2c->usi_ctl); 236*37b8eb37SSimon Glass i2c_ctl &= ~HSI2C_SW_RST; 237*37b8eb37SSimon Glass writel(i2c_ctl, &i2c->usi_ctl); 238*37b8eb37SSimon Glass 239*37b8eb37SSimon Glass /* Initialize the configure registers */ 240*37b8eb37SSimon Glass hsi2c_ch_init(i2c_bus); 241*37b8eb37SSimon Glass } 242*37b8eb37SSimon Glass 243*37b8eb37SSimon Glass /* 244*37b8eb37SSimon Glass * Poll the appropriate bit of the fifo status register until the interface is 245*37b8eb37SSimon Glass * ready to process the next byte or timeout expires. 246*37b8eb37SSimon Glass * 247*37b8eb37SSimon Glass * In addition to the FIFO status register this function also polls the 248*37b8eb37SSimon Glass * interrupt status register to be able to detect unexpected transaction 249*37b8eb37SSimon Glass * completion. 250*37b8eb37SSimon Glass * 251*37b8eb37SSimon Glass * When FIFO is ready to process the next byte, this function returns I2C_OK. 252*37b8eb37SSimon Glass * If in course of polling the INT_I2C assertion is detected, the function 253*37b8eb37SSimon Glass * returns I2C_NOK. If timeout happens before any of the above conditions is 254*37b8eb37SSimon Glass * met - the function returns I2C_NOK_TOUT; 255*37b8eb37SSimon Glass 256*37b8eb37SSimon Glass * @param i2c: pointer to the appropriate i2c register bank. 257*37b8eb37SSimon Glass * @param rx_transfer: set to True if the receive transaction is in progress. 258*37b8eb37SSimon Glass * @return: as described above. 259*37b8eb37SSimon Glass */ 260*37b8eb37SSimon Glass static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) 261*37b8eb37SSimon Glass { 262*37b8eb37SSimon Glass u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; 263*37b8eb37SSimon Glass int i = HSI2C_TIMEOUT_US; 264*37b8eb37SSimon Glass 265*37b8eb37SSimon Glass while (readl(&i2c->usi_fifo_stat) & fifo_bit) { 266*37b8eb37SSimon Glass if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { 267*37b8eb37SSimon Glass /* 268*37b8eb37SSimon Glass * There is a chance that assertion of 269*37b8eb37SSimon Glass * HSI2C_INT_I2C_EN and deassertion of 270*37b8eb37SSimon Glass * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's 271*37b8eb37SSimon Glass * give FIFO status priority and check it one more 272*37b8eb37SSimon Glass * time before reporting interrupt. The interrupt will 273*37b8eb37SSimon Glass * be reported next time this function is called. 274*37b8eb37SSimon Glass */ 275*37b8eb37SSimon Glass if (rx_transfer && 276*37b8eb37SSimon Glass !(readl(&i2c->usi_fifo_stat) & fifo_bit)) 277*37b8eb37SSimon Glass break; 278*37b8eb37SSimon Glass return I2C_NOK; 279*37b8eb37SSimon Glass } 280*37b8eb37SSimon Glass if (!i--) { 281*37b8eb37SSimon Glass debug("%s: FIFO polling timeout!\n", __func__); 282*37b8eb37SSimon Glass return I2C_NOK_TOUT; 283*37b8eb37SSimon Glass } 284*37b8eb37SSimon Glass udelay(1); 285*37b8eb37SSimon Glass } 286*37b8eb37SSimon Glass return I2C_OK; 287*37b8eb37SSimon Glass } 288*37b8eb37SSimon Glass 289*37b8eb37SSimon Glass /* 290*37b8eb37SSimon Glass * Preapre hsi2c transaction, either read or write. 291*37b8eb37SSimon Glass * 292*37b8eb37SSimon Glass * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of 293*37b8eb37SSimon Glass * the 5420 UM. 294*37b8eb37SSimon Glass * 295*37b8eb37SSimon Glass * @param i2c: pointer to the appropriate i2c register bank. 296*37b8eb37SSimon Glass * @param chip: slave address on the i2c bus (with read/write bit exlcuded) 297*37b8eb37SSimon Glass * @param len: number of bytes expected to be sent or received 298*37b8eb37SSimon Glass * @param rx_transfer: set to true for receive transactions 299*37b8eb37SSimon Glass * @param: issue_stop: set to true if i2c stop condition should be generated 300*37b8eb37SSimon Glass * after this transaction. 301*37b8eb37SSimon Glass * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, 302*37b8eb37SSimon Glass * I2C_OK otherwise. 303*37b8eb37SSimon Glass */ 304*37b8eb37SSimon Glass static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, 305*37b8eb37SSimon Glass u8 chip, 306*37b8eb37SSimon Glass u16 len, 307*37b8eb37SSimon Glass bool rx_transfer, 308*37b8eb37SSimon Glass bool issue_stop) 309*37b8eb37SSimon Glass { 310*37b8eb37SSimon Glass u32 conf; 311*37b8eb37SSimon Glass 312*37b8eb37SSimon Glass conf = len | HSI2C_MASTER_RUN; 313*37b8eb37SSimon Glass 314*37b8eb37SSimon Glass if (issue_stop) 315*37b8eb37SSimon Glass conf |= HSI2C_STOP_AFTER_TRANS; 316*37b8eb37SSimon Glass 317*37b8eb37SSimon Glass /* Clear to enable Timeout */ 318*37b8eb37SSimon Glass writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); 319*37b8eb37SSimon Glass 320*37b8eb37SSimon Glass /* Set slave address */ 321*37b8eb37SSimon Glass writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); 322*37b8eb37SSimon Glass 323*37b8eb37SSimon Glass if (rx_transfer) { 324*37b8eb37SSimon Glass /* i2c master, read transaction */ 325*37b8eb37SSimon Glass writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 326*37b8eb37SSimon Glass &i2c->usi_ctl); 327*37b8eb37SSimon Glass 328*37b8eb37SSimon Glass /* read up to len bytes, stop after transaction is finished */ 329*37b8eb37SSimon Glass writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); 330*37b8eb37SSimon Glass } else { 331*37b8eb37SSimon Glass /* i2c master, write transaction */ 332*37b8eb37SSimon Glass writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 333*37b8eb37SSimon Glass &i2c->usi_ctl); 334*37b8eb37SSimon Glass 335*37b8eb37SSimon Glass /* write up to len bytes, stop after transaction is finished */ 336*37b8eb37SSimon Glass writel(conf, &i2c->usi_auto_conf); 337*37b8eb37SSimon Glass } 338*37b8eb37SSimon Glass 339*37b8eb37SSimon Glass /* Reset all pending interrupt status bits we care about, if any */ 340*37b8eb37SSimon Glass writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); 341*37b8eb37SSimon Glass 342*37b8eb37SSimon Glass return I2C_OK; 343*37b8eb37SSimon Glass } 344*37b8eb37SSimon Glass 345*37b8eb37SSimon Glass /* 346*37b8eb37SSimon Glass * Wait while i2c bus is settling down (mostly stop gets completed). 347*37b8eb37SSimon Glass */ 348*37b8eb37SSimon Glass static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) 349*37b8eb37SSimon Glass { 350*37b8eb37SSimon Glass int i = HSI2C_TIMEOUT_US; 351*37b8eb37SSimon Glass 352*37b8eb37SSimon Glass while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { 353*37b8eb37SSimon Glass if (!i--) { 354*37b8eb37SSimon Glass debug("%s: bus busy\n", __func__); 355*37b8eb37SSimon Glass return I2C_NOK_TOUT; 356*37b8eb37SSimon Glass } 357*37b8eb37SSimon Glass udelay(1); 358*37b8eb37SSimon Glass } 359*37b8eb37SSimon Glass return I2C_OK; 360*37b8eb37SSimon Glass } 361*37b8eb37SSimon Glass 362*37b8eb37SSimon Glass static int hsi2c_write(struct exynos5_hsi2c *i2c, 363*37b8eb37SSimon Glass unsigned char chip, 364*37b8eb37SSimon Glass unsigned char addr[], 365*37b8eb37SSimon Glass unsigned char alen, 366*37b8eb37SSimon Glass unsigned char data[], 367*37b8eb37SSimon Glass unsigned short len, 368*37b8eb37SSimon Glass bool issue_stop) 369*37b8eb37SSimon Glass { 370*37b8eb37SSimon Glass int i, rv = 0; 371*37b8eb37SSimon Glass 372*37b8eb37SSimon Glass if (!(len + alen)) { 373*37b8eb37SSimon Glass /* Writes of zero length not supported in auto mode. */ 374*37b8eb37SSimon Glass debug("%s: zero length writes not supported\n", __func__); 375*37b8eb37SSimon Glass return I2C_NOK; 376*37b8eb37SSimon Glass } 377*37b8eb37SSimon Glass 378*37b8eb37SSimon Glass rv = hsi2c_prepare_transaction 379*37b8eb37SSimon Glass (i2c, chip, len + alen, false, issue_stop); 380*37b8eb37SSimon Glass if (rv != I2C_OK) 381*37b8eb37SSimon Glass return rv; 382*37b8eb37SSimon Glass 383*37b8eb37SSimon Glass /* Move address, if any, and the data, if any, into the FIFO. */ 384*37b8eb37SSimon Glass for (i = 0; i < alen; i++) { 385*37b8eb37SSimon Glass rv = hsi2c_poll_fifo(i2c, false); 386*37b8eb37SSimon Glass if (rv != I2C_OK) { 387*37b8eb37SSimon Glass debug("%s: address write failed\n", __func__); 388*37b8eb37SSimon Glass goto write_error; 389*37b8eb37SSimon Glass } 390*37b8eb37SSimon Glass writel(addr[i], &i2c->usi_txdata); 391*37b8eb37SSimon Glass } 392*37b8eb37SSimon Glass 393*37b8eb37SSimon Glass for (i = 0; i < len; i++) { 394*37b8eb37SSimon Glass rv = hsi2c_poll_fifo(i2c, false); 395*37b8eb37SSimon Glass if (rv != I2C_OK) { 396*37b8eb37SSimon Glass debug("%s: data write failed\n", __func__); 397*37b8eb37SSimon Glass goto write_error; 398*37b8eb37SSimon Glass } 399*37b8eb37SSimon Glass writel(data[i], &i2c->usi_txdata); 400*37b8eb37SSimon Glass } 401*37b8eb37SSimon Glass 402*37b8eb37SSimon Glass rv = hsi2c_wait_for_trx(i2c); 403*37b8eb37SSimon Glass 404*37b8eb37SSimon Glass write_error: 405*37b8eb37SSimon Glass if (issue_stop) { 406*37b8eb37SSimon Glass int tmp_ret = hsi2c_wait_while_busy(i2c); 407*37b8eb37SSimon Glass if (rv == I2C_OK) 408*37b8eb37SSimon Glass rv = tmp_ret; 409*37b8eb37SSimon Glass } 410*37b8eb37SSimon Glass 411*37b8eb37SSimon Glass writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 412*37b8eb37SSimon Glass return rv; 413*37b8eb37SSimon Glass } 414*37b8eb37SSimon Glass 415*37b8eb37SSimon Glass static int hsi2c_read(struct exynos5_hsi2c *i2c, 416*37b8eb37SSimon Glass unsigned char chip, 417*37b8eb37SSimon Glass unsigned char addr[], 418*37b8eb37SSimon Glass unsigned char alen, 419*37b8eb37SSimon Glass unsigned char data[], 420*37b8eb37SSimon Glass unsigned short len) 421*37b8eb37SSimon Glass { 422*37b8eb37SSimon Glass int i, rv, tmp_ret; 423*37b8eb37SSimon Glass bool drop_data = false; 424*37b8eb37SSimon Glass 425*37b8eb37SSimon Glass if (!len) { 426*37b8eb37SSimon Glass /* Reads of zero length not supported in auto mode. */ 427*37b8eb37SSimon Glass debug("%s: zero length read adjusted\n", __func__); 428*37b8eb37SSimon Glass drop_data = true; 429*37b8eb37SSimon Glass len = 1; 430*37b8eb37SSimon Glass } 431*37b8eb37SSimon Glass 432*37b8eb37SSimon Glass if (alen) { 433*37b8eb37SSimon Glass /* Internal register adress needs to be written first. */ 434*37b8eb37SSimon Glass rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); 435*37b8eb37SSimon Glass if (rv != I2C_OK) 436*37b8eb37SSimon Glass return rv; 437*37b8eb37SSimon Glass } 438*37b8eb37SSimon Glass 439*37b8eb37SSimon Glass rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); 440*37b8eb37SSimon Glass 441*37b8eb37SSimon Glass if (rv != I2C_OK) 442*37b8eb37SSimon Glass return rv; 443*37b8eb37SSimon Glass 444*37b8eb37SSimon Glass for (i = 0; i < len; i++) { 445*37b8eb37SSimon Glass rv = hsi2c_poll_fifo(i2c, true); 446*37b8eb37SSimon Glass if (rv != I2C_OK) 447*37b8eb37SSimon Glass goto read_err; 448*37b8eb37SSimon Glass if (drop_data) 449*37b8eb37SSimon Glass continue; 450*37b8eb37SSimon Glass data[i] = readl(&i2c->usi_rxdata); 451*37b8eb37SSimon Glass } 452*37b8eb37SSimon Glass 453*37b8eb37SSimon Glass rv = hsi2c_wait_for_trx(i2c); 454*37b8eb37SSimon Glass 455*37b8eb37SSimon Glass read_err: 456*37b8eb37SSimon Glass tmp_ret = hsi2c_wait_while_busy(i2c); 457*37b8eb37SSimon Glass if (rv == I2C_OK) 458*37b8eb37SSimon Glass rv = tmp_ret; 459*37b8eb37SSimon Glass 460*37b8eb37SSimon Glass writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 461*37b8eb37SSimon Glass return rv; 462*37b8eb37SSimon Glass } 463*37b8eb37SSimon Glass 464*37b8eb37SSimon Glass static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 465*37b8eb37SSimon Glass int nmsgs) 466*37b8eb37SSimon Glass { 467*37b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 468*37b8eb37SSimon Glass struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 469*37b8eb37SSimon Glass int ret; 470*37b8eb37SSimon Glass 471*37b8eb37SSimon Glass for (; nmsgs > 0; nmsgs--, msg++) { 472*37b8eb37SSimon Glass if (msg->flags & I2C_M_RD) { 473*37b8eb37SSimon Glass ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf, 474*37b8eb37SSimon Glass msg->len); 475*37b8eb37SSimon Glass } else { 476*37b8eb37SSimon Glass ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf, 477*37b8eb37SSimon Glass msg->len, true); 478*37b8eb37SSimon Glass } 479*37b8eb37SSimon Glass if (ret) { 480*37b8eb37SSimon Glass exynos5_i2c_reset(i2c_bus); 481*37b8eb37SSimon Glass return -EREMOTEIO; 482*37b8eb37SSimon Glass } 483*37b8eb37SSimon Glass } 484*37b8eb37SSimon Glass 485*37b8eb37SSimon Glass return 0; 486*37b8eb37SSimon Glass } 487*37b8eb37SSimon Glass 488*37b8eb37SSimon Glass static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 489*37b8eb37SSimon Glass { 490*37b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 491*37b8eb37SSimon Glass 492*37b8eb37SSimon Glass i2c_bus->clock_frequency = speed; 493*37b8eb37SSimon Glass 494*37b8eb37SSimon Glass if (hsi2c_get_clk_details(i2c_bus)) 495*37b8eb37SSimon Glass return -EFAULT; 496*37b8eb37SSimon Glass hsi2c_ch_init(i2c_bus); 497*37b8eb37SSimon Glass 498*37b8eb37SSimon Glass return 0; 499*37b8eb37SSimon Glass } 500*37b8eb37SSimon Glass 501*37b8eb37SSimon Glass static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) 502*37b8eb37SSimon Glass { 503*37b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 504*37b8eb37SSimon Glass uchar buf[1]; 505*37b8eb37SSimon Glass int ret; 506*37b8eb37SSimon Glass 507*37b8eb37SSimon Glass buf[0] = 0; 508*37b8eb37SSimon Glass 509*37b8eb37SSimon Glass /* 510*37b8eb37SSimon Glass * What is needed is to send the chip address and verify that the 511*37b8eb37SSimon Glass * address was <ACK>ed (i.e. there was a chip at that address which 512*37b8eb37SSimon Glass * drove the data line low). 513*37b8eb37SSimon Glass */ 514*37b8eb37SSimon Glass ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1); 515*37b8eb37SSimon Glass 516*37b8eb37SSimon Glass return ret != I2C_OK; 517*37b8eb37SSimon Glass } 518*37b8eb37SSimon Glass 519*37b8eb37SSimon Glass static int s3c_i2c_ofdata_to_platdata(struct udevice *dev) 520*37b8eb37SSimon Glass { 521*37b8eb37SSimon Glass const void *blob = gd->fdt_blob; 522*37b8eb37SSimon Glass struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 523*37b8eb37SSimon Glass int node; 524*37b8eb37SSimon Glass 525*37b8eb37SSimon Glass node = dev->of_offset; 526*37b8eb37SSimon Glass 527*37b8eb37SSimon Glass i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev); 528*37b8eb37SSimon Glass 529*37b8eb37SSimon Glass i2c_bus->id = pinmux_decode_periph_id(blob, node); 530*37b8eb37SSimon Glass 531*37b8eb37SSimon Glass i2c_bus->clock_frequency = fdtdec_get_int(blob, node, 532*37b8eb37SSimon Glass "clock-frequency", 100000); 533*37b8eb37SSimon Glass i2c_bus->node = node; 534*37b8eb37SSimon Glass i2c_bus->bus_num = dev->seq; 535*37b8eb37SSimon Glass 536*37b8eb37SSimon Glass exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE); 537*37b8eb37SSimon Glass 538*37b8eb37SSimon Glass i2c_bus->active = true; 539*37b8eb37SSimon Glass 540*37b8eb37SSimon Glass return 0; 541*37b8eb37SSimon Glass } 542*37b8eb37SSimon Glass 543*37b8eb37SSimon Glass static const struct dm_i2c_ops exynos_hs_i2c_ops = { 544*37b8eb37SSimon Glass .xfer = exynos_hs_i2c_xfer, 545*37b8eb37SSimon Glass .probe_chip = s3c24x0_i2c_probe, 546*37b8eb37SSimon Glass .set_bus_speed = s3c24x0_i2c_set_bus_speed, 547*37b8eb37SSimon Glass }; 548*37b8eb37SSimon Glass 549*37b8eb37SSimon Glass static const struct udevice_id exynos_hs_i2c_ids[] = { 550*37b8eb37SSimon Glass { .compatible = "samsung,exynos5-hsi2c" }, 551*37b8eb37SSimon Glass { } 552*37b8eb37SSimon Glass }; 553*37b8eb37SSimon Glass 554*37b8eb37SSimon Glass U_BOOT_DRIVER(hs_i2c) = { 555*37b8eb37SSimon Glass .name = "i2c_s3c_hs", 556*37b8eb37SSimon Glass .id = UCLASS_I2C, 557*37b8eb37SSimon Glass .of_match = exynos_hs_i2c_ids, 558*37b8eb37SSimon Glass .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, 559*37b8eb37SSimon Glass .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), 560*37b8eb37SSimon Glass .ops = &exynos_hs_i2c_ops, 561*37b8eb37SSimon Glass }; 562