1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <i2c.h> 11 #include <pci.h> 12 #include <asm/io.h> 13 #include "designware_i2c.h" 14 15 struct dw_scl_sda_cfg { 16 u32 ss_hcnt; 17 u32 fs_hcnt; 18 u32 ss_lcnt; 19 u32 fs_lcnt; 20 u32 sda_hold; 21 }; 22 23 #ifdef CONFIG_X86 24 /* BayTrail HCNT/LCNT/SDA hold time */ 25 static struct dw_scl_sda_cfg byt_config = { 26 .ss_hcnt = 0x200, 27 .fs_hcnt = 0x55, 28 .ss_lcnt = 0x200, 29 .fs_lcnt = 0x99, 30 .sda_hold = 0x6, 31 }; 32 #endif 33 34 struct dw_i2c { 35 struct i2c_regs *regs; 36 struct dw_scl_sda_cfg *scl_sda_cfg; 37 }; 38 39 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) 40 { 41 u32 ena = enable ? IC_ENABLE_0B : 0; 42 int timeout = 100; 43 44 do { 45 writel(ena, &i2c_base->ic_enable); 46 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) 47 return; 48 49 /* 50 * Wait 10 times the signaling period of the highest I2C 51 * transfer supported by the driver (for 400KHz this is 52 * 25us) as described in the DesignWare I2C databook. 53 */ 54 udelay(25); 55 } while (timeout--); 56 57 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); 58 } 59 60 /* 61 * i2c_set_bus_speed - Set the i2c speed 62 * @speed: required i2c speed 63 * 64 * Set the i2c speed. 65 */ 66 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, 67 struct dw_scl_sda_cfg *scl_sda_cfg, 68 unsigned int speed) 69 { 70 unsigned int cntl; 71 unsigned int hcnt, lcnt; 72 int i2c_spd; 73 74 if (speed >= I2C_MAX_SPEED) 75 i2c_spd = IC_SPEED_MODE_MAX; 76 else if (speed >= I2C_FAST_SPEED) 77 i2c_spd = IC_SPEED_MODE_FAST; 78 else 79 i2c_spd = IC_SPEED_MODE_STANDARD; 80 81 /* to set speed cltr must be disabled */ 82 dw_i2c_enable(i2c_base, false); 83 84 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); 85 86 switch (i2c_spd) { 87 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */ 88 case IC_SPEED_MODE_MAX: 89 cntl |= IC_CON_SPD_SS; 90 if (scl_sda_cfg) { 91 hcnt = scl_sda_cfg->fs_hcnt; 92 lcnt = scl_sda_cfg->fs_lcnt; 93 } else { 94 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; 95 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; 96 } 97 writel(hcnt, &i2c_base->ic_hs_scl_hcnt); 98 writel(lcnt, &i2c_base->ic_hs_scl_lcnt); 99 break; 100 #endif 101 102 case IC_SPEED_MODE_STANDARD: 103 cntl |= IC_CON_SPD_SS; 104 if (scl_sda_cfg) { 105 hcnt = scl_sda_cfg->ss_hcnt; 106 lcnt = scl_sda_cfg->ss_lcnt; 107 } else { 108 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; 109 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; 110 } 111 writel(hcnt, &i2c_base->ic_ss_scl_hcnt); 112 writel(lcnt, &i2c_base->ic_ss_scl_lcnt); 113 break; 114 115 case IC_SPEED_MODE_FAST: 116 default: 117 cntl |= IC_CON_SPD_FS; 118 if (scl_sda_cfg) { 119 hcnt = scl_sda_cfg->fs_hcnt; 120 lcnt = scl_sda_cfg->fs_lcnt; 121 } else { 122 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; 123 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; 124 } 125 writel(hcnt, &i2c_base->ic_fs_scl_hcnt); 126 writel(lcnt, &i2c_base->ic_fs_scl_lcnt); 127 break; 128 } 129 130 writel(cntl, &i2c_base->ic_con); 131 132 /* Configure SDA Hold Time if required */ 133 if (scl_sda_cfg) 134 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold); 135 136 /* Enable back i2c now speed set */ 137 dw_i2c_enable(i2c_base, true); 138 139 return 0; 140 } 141 142 /* 143 * i2c_setaddress - Sets the target slave address 144 * @i2c_addr: target i2c address 145 * 146 * Sets the target slave address. 147 */ 148 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr) 149 { 150 /* Disable i2c */ 151 dw_i2c_enable(i2c_base, false); 152 153 writel(i2c_addr, &i2c_base->ic_tar); 154 155 /* Enable i2c */ 156 dw_i2c_enable(i2c_base, true); 157 } 158 159 /* 160 * i2c_flush_rxfifo - Flushes the i2c RX FIFO 161 * 162 * Flushes the i2c RX FIFO 163 */ 164 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base) 165 { 166 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) 167 readl(&i2c_base->ic_cmd_data); 168 } 169 170 /* 171 * i2c_wait_for_bb - Waits for bus busy 172 * 173 * Waits for bus busy 174 */ 175 static int i2c_wait_for_bb(struct i2c_regs *i2c_base) 176 { 177 unsigned long start_time_bb = get_timer(0); 178 179 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) || 180 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) { 181 182 /* Evaluate timeout */ 183 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) 184 return 1; 185 } 186 187 return 0; 188 } 189 190 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr, 191 int alen) 192 { 193 if (i2c_wait_for_bb(i2c_base)) 194 return 1; 195 196 i2c_setaddress(i2c_base, chip); 197 while (alen) { 198 alen--; 199 /* high byte address going out first */ 200 writel((addr >> (alen * 8)) & 0xff, 201 &i2c_base->ic_cmd_data); 202 } 203 return 0; 204 } 205 206 static int i2c_xfer_finish(struct i2c_regs *i2c_base) 207 { 208 ulong start_stop_det = get_timer(0); 209 210 while (1) { 211 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) { 212 readl(&i2c_base->ic_clr_stop_det); 213 break; 214 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { 215 break; 216 } 217 } 218 219 if (i2c_wait_for_bb(i2c_base)) { 220 printf("Timed out waiting for bus\n"); 221 return 1; 222 } 223 224 i2c_flush_rxfifo(i2c_base); 225 226 return 0; 227 } 228 229 /* 230 * i2c_read - Read from i2c memory 231 * @chip: target i2c address 232 * @addr: address to read from 233 * @alen: 234 * @buffer: buffer for read data 235 * @len: no of bytes to be read 236 * 237 * Read from i2c memory. 238 */ 239 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, 240 int alen, u8 *buffer, int len) 241 { 242 unsigned long start_time_rx; 243 244 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 245 /* 246 * EEPROM chips that implement "address overflow" are ones 247 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 248 * address and the extra bits end up in the "chip address" 249 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 250 * four 256 byte chips. 251 * 252 * Note that we consider the length of the address field to 253 * still be one byte because the extra address bits are 254 * hidden in the chip address. 255 */ 256 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 257 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 258 259 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 260 addr); 261 #endif 262 263 if (i2c_xfer_init(i2c_base, dev, addr, alen)) 264 return 1; 265 266 start_time_rx = get_timer(0); 267 while (len) { 268 if (len == 1) 269 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); 270 else 271 writel(IC_CMD, &i2c_base->ic_cmd_data); 272 273 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { 274 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); 275 len--; 276 start_time_rx = get_timer(0); 277 278 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { 279 return 1; 280 } 281 } 282 283 return i2c_xfer_finish(i2c_base); 284 } 285 286 /* 287 * i2c_write - Write to i2c memory 288 * @chip: target i2c address 289 * @addr: address to read from 290 * @alen: 291 * @buffer: buffer for read data 292 * @len: no of bytes to be read 293 * 294 * Write to i2c memory. 295 */ 296 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr, 297 int alen, u8 *buffer, int len) 298 { 299 int nb = len; 300 unsigned long start_time_tx; 301 302 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 303 /* 304 * EEPROM chips that implement "address overflow" are ones 305 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 306 * address and the extra bits end up in the "chip address" 307 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 308 * four 256 byte chips. 309 * 310 * Note that we consider the length of the address field to 311 * still be one byte because the extra address bits are 312 * hidden in the chip address. 313 */ 314 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 315 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 316 317 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 318 addr); 319 #endif 320 321 if (i2c_xfer_init(i2c_base, dev, addr, alen)) 322 return 1; 323 324 start_time_tx = get_timer(0); 325 while (len) { 326 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) { 327 if (--len == 0) { 328 writel(*buffer | IC_STOP, 329 &i2c_base->ic_cmd_data); 330 } else { 331 writel(*buffer, &i2c_base->ic_cmd_data); 332 } 333 buffer++; 334 start_time_tx = get_timer(0); 335 336 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { 337 printf("Timed out. i2c write Failed\n"); 338 return 1; 339 } 340 } 341 342 return i2c_xfer_finish(i2c_base); 343 } 344 345 /* 346 * __dw_i2c_init - Init function 347 * @speed: required i2c speed 348 * @slaveaddr: slave address for the device 349 * 350 * Initialization function. 351 */ 352 static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr) 353 { 354 /* Disable i2c */ 355 dw_i2c_enable(i2c_base, false); 356 357 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); 358 writel(IC_RX_TL, &i2c_base->ic_rx_tl); 359 writel(IC_TX_TL, &i2c_base->ic_tx_tl); 360 writel(IC_STOP_DET, &i2c_base->ic_intr_mask); 361 #ifndef CONFIG_DM_I2C 362 __dw_i2c_set_bus_speed(i2c_base, NULL, speed); 363 writel(slaveaddr, &i2c_base->ic_sar); 364 #endif 365 366 /* Enable i2c */ 367 dw_i2c_enable(i2c_base, true); 368 } 369 370 #ifndef CONFIG_DM_I2C 371 /* 372 * The legacy I2C functions. These need to get removed once 373 * all users of this driver are converted to DM. 374 */ 375 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) 376 { 377 switch (adap->hwadapnr) { 378 #if CONFIG_SYS_I2C_BUS_MAX >= 4 379 case 3: 380 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; 381 #endif 382 #if CONFIG_SYS_I2C_BUS_MAX >= 3 383 case 2: 384 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; 385 #endif 386 #if CONFIG_SYS_I2C_BUS_MAX >= 2 387 case 1: 388 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; 389 #endif 390 case 0: 391 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; 392 default: 393 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr); 394 } 395 396 return NULL; 397 } 398 399 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, 400 unsigned int speed) 401 { 402 adap->speed = speed; 403 return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed); 404 } 405 406 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 407 { 408 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr); 409 } 410 411 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, 412 int alen, u8 *buffer, int len) 413 { 414 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len); 415 } 416 417 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, 418 int alen, u8 *buffer, int len) 419 { 420 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len); 421 } 422 423 /* dw_i2c_probe - Probe the i2c chip */ 424 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) 425 { 426 struct i2c_regs *i2c_base = i2c_get_base(adap); 427 u32 tmp; 428 int ret; 429 430 /* 431 * Try to read the first location of the chip. 432 */ 433 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1); 434 if (ret) 435 dw_i2c_init(adap, adap->speed, adap->slaveaddr); 436 437 return ret; 438 } 439 440 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 441 dw_i2c_write, dw_i2c_set_bus_speed, 442 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 443 444 #if CONFIG_SYS_I2C_BUS_MAX >= 2 445 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 446 dw_i2c_write, dw_i2c_set_bus_speed, 447 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) 448 #endif 449 450 #if CONFIG_SYS_I2C_BUS_MAX >= 3 451 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 452 dw_i2c_write, dw_i2c_set_bus_speed, 453 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) 454 #endif 455 456 #if CONFIG_SYS_I2C_BUS_MAX >= 4 457 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 458 dw_i2c_write, dw_i2c_set_bus_speed, 459 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) 460 #endif 461 462 #else /* CONFIG_DM_I2C */ 463 /* The DM I2C functions */ 464 465 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 466 int nmsgs) 467 { 468 struct dw_i2c *i2c = dev_get_priv(bus); 469 int ret; 470 471 debug("i2c_xfer: %d messages\n", nmsgs); 472 for (; nmsgs > 0; nmsgs--, msg++) { 473 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 474 if (msg->flags & I2C_M_RD) { 475 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0, 476 msg->buf, msg->len); 477 } else { 478 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0, 479 msg->buf, msg->len); 480 } 481 if (ret) { 482 debug("i2c_write: error sending\n"); 483 return -EREMOTEIO; 484 } 485 } 486 487 return 0; 488 } 489 490 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 491 { 492 struct dw_i2c *i2c = dev_get_priv(bus); 493 494 return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed); 495 } 496 497 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, 498 uint chip_flags) 499 { 500 struct dw_i2c *i2c = dev_get_priv(bus); 501 struct i2c_regs *i2c_base = i2c->regs; 502 u32 tmp; 503 int ret; 504 505 /* Try to read the first location of the chip */ 506 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1); 507 if (ret) 508 __dw_i2c_init(i2c_base, 0, 0); 509 510 return ret; 511 } 512 513 static int designware_i2c_probe(struct udevice *bus) 514 { 515 struct dw_i2c *priv = dev_get_priv(bus); 516 517 if (device_is_on_pci_bus(bus)) { 518 #ifdef CONFIG_DM_PCI 519 /* Save base address from PCI BAR */ 520 priv->regs = (struct i2c_regs *) 521 dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); 522 #ifdef CONFIG_X86 523 /* Use BayTrail specific timing values */ 524 priv->scl_sda_cfg = &byt_config; 525 #endif 526 #endif 527 } else { 528 priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus); 529 } 530 531 __dw_i2c_init(priv->regs, 0, 0); 532 533 return 0; 534 } 535 536 static int designware_i2c_bind(struct udevice *dev) 537 { 538 static int num_cards; 539 char name[20]; 540 541 /* Create a unique device name for PCI type devices */ 542 if (device_is_on_pci_bus(dev)) { 543 /* 544 * ToDo: 545 * Setting req_seq in the driver is probably not recommended. 546 * But without a DT alias the number is not configured. And 547 * using this driver is impossible for PCIe I2C devices. 548 * This can be removed, once a better (correct) way for this 549 * is found and implemented. 550 */ 551 dev->req_seq = num_cards; 552 sprintf(name, "i2c_designware#%u", num_cards++); 553 device_set_name(dev, name); 554 } 555 556 return 0; 557 } 558 559 static const struct dm_i2c_ops designware_i2c_ops = { 560 .xfer = designware_i2c_xfer, 561 .probe_chip = designware_i2c_probe_chip, 562 .set_bus_speed = designware_i2c_set_bus_speed, 563 }; 564 565 static const struct udevice_id designware_i2c_ids[] = { 566 { .compatible = "snps,designware-i2c" }, 567 { } 568 }; 569 570 U_BOOT_DRIVER(i2c_designware) = { 571 .name = "i2c_designware", 572 .id = UCLASS_I2C, 573 .of_match = designware_i2c_ids, 574 .bind = designware_i2c_bind, 575 .probe = designware_i2c_probe, 576 .priv_auto_alloc_size = sizeof(struct dw_i2c), 577 .ops = &designware_i2c_ops, 578 }; 579 580 #ifdef CONFIG_X86 581 static struct pci_device_id designware_pci_supported[] = { 582 /* Intel BayTrail has 7 I2C controller located on the PCI bus */ 583 { PCI_VDEVICE(INTEL, 0x0f41) }, 584 { PCI_VDEVICE(INTEL, 0x0f42) }, 585 { PCI_VDEVICE(INTEL, 0x0f43) }, 586 { PCI_VDEVICE(INTEL, 0x0f44) }, 587 { PCI_VDEVICE(INTEL, 0x0f45) }, 588 { PCI_VDEVICE(INTEL, 0x0f46) }, 589 { PCI_VDEVICE(INTEL, 0x0f47) }, 590 {}, 591 }; 592 593 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported); 594 #endif 595 596 #endif /* CONFIG_DM_I2C */ 597