1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include "designware_i2c.h" 11 12 #ifdef CONFIG_I2C_MULTI_BUS 13 static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX]; 14 static unsigned int current_bus = 0; 15 #endif 16 17 static struct i2c_regs *i2c_regs_p = 18 (struct i2c_regs *)CONFIG_SYS_I2C_BASE; 19 20 /* 21 * set_speed - Set the i2c speed mode (standard, high, fast) 22 * @i2c_spd: required i2c speed mode 23 * 24 * Set the i2c speed mode (standard, high, fast) 25 */ 26 static void set_speed(int i2c_spd) 27 { 28 unsigned int cntl; 29 unsigned int hcnt, lcnt; 30 unsigned int enbl; 31 32 /* to set speed cltr must be disabled */ 33 enbl = readl(&i2c_regs_p->ic_enable); 34 enbl &= ~IC_ENABLE_0B; 35 writel(enbl, &i2c_regs_p->ic_enable); 36 37 cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK)); 38 39 switch (i2c_spd) { 40 case IC_SPEED_MODE_MAX: 41 cntl |= IC_CON_SPD_HS; 42 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; 43 writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt); 44 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; 45 writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt); 46 break; 47 48 case IC_SPEED_MODE_STANDARD: 49 cntl |= IC_CON_SPD_SS; 50 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; 51 writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt); 52 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; 53 writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt); 54 break; 55 56 case IC_SPEED_MODE_FAST: 57 default: 58 cntl |= IC_CON_SPD_FS; 59 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; 60 writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt); 61 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; 62 writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt); 63 break; 64 } 65 66 writel(cntl, &i2c_regs_p->ic_con); 67 68 /* Enable back i2c now speed set */ 69 enbl |= IC_ENABLE_0B; 70 writel(enbl, &i2c_regs_p->ic_enable); 71 } 72 73 /* 74 * i2c_set_bus_speed - Set the i2c speed 75 * @speed: required i2c speed 76 * 77 * Set the i2c speed. 78 */ 79 int i2c_set_bus_speed(int speed) 80 { 81 if (speed >= I2C_MAX_SPEED) 82 set_speed(IC_SPEED_MODE_MAX); 83 else if (speed >= I2C_FAST_SPEED) 84 set_speed(IC_SPEED_MODE_FAST); 85 else 86 set_speed(IC_SPEED_MODE_STANDARD); 87 88 return 0; 89 } 90 91 /* 92 * i2c_get_bus_speed - Gets the i2c speed 93 * 94 * Gets the i2c speed. 95 */ 96 int i2c_get_bus_speed(void) 97 { 98 u32 cntl; 99 100 cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK); 101 102 if (cntl == IC_CON_SPD_HS) 103 return I2C_MAX_SPEED; 104 else if (cntl == IC_CON_SPD_FS) 105 return I2C_FAST_SPEED; 106 else if (cntl == IC_CON_SPD_SS) 107 return I2C_STANDARD_SPEED; 108 109 return 0; 110 } 111 112 /* 113 * i2c_init - Init function 114 * @speed: required i2c speed 115 * @slaveadd: slave address for the device 116 * 117 * Initialization function. 118 */ 119 void i2c_init(int speed, int slaveadd) 120 { 121 unsigned int enbl; 122 123 /* Disable i2c */ 124 enbl = readl(&i2c_regs_p->ic_enable); 125 enbl &= ~IC_ENABLE_0B; 126 writel(enbl, &i2c_regs_p->ic_enable); 127 128 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con); 129 writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl); 130 writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl); 131 i2c_set_bus_speed(speed); 132 writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask); 133 writel(slaveadd, &i2c_regs_p->ic_sar); 134 135 /* Enable i2c */ 136 enbl = readl(&i2c_regs_p->ic_enable); 137 enbl |= IC_ENABLE_0B; 138 writel(enbl, &i2c_regs_p->ic_enable); 139 140 #ifdef CONFIG_I2C_MULTI_BUS 141 bus_initialized[current_bus] = 1; 142 #endif 143 } 144 145 /* 146 * i2c_setaddress - Sets the target slave address 147 * @i2c_addr: target i2c address 148 * 149 * Sets the target slave address. 150 */ 151 static void i2c_setaddress(unsigned int i2c_addr) 152 { 153 unsigned int enbl; 154 155 /* Disable i2c */ 156 enbl = readl(&i2c_regs_p->ic_enable); 157 enbl &= ~IC_ENABLE_0B; 158 writel(enbl, &i2c_regs_p->ic_enable); 159 160 writel(i2c_addr, &i2c_regs_p->ic_tar); 161 162 /* Enable i2c */ 163 enbl = readl(&i2c_regs_p->ic_enable); 164 enbl |= IC_ENABLE_0B; 165 writel(enbl, &i2c_regs_p->ic_enable); 166 } 167 168 /* 169 * i2c_flush_rxfifo - Flushes the i2c RX FIFO 170 * 171 * Flushes the i2c RX FIFO 172 */ 173 static void i2c_flush_rxfifo(void) 174 { 175 while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) 176 readl(&i2c_regs_p->ic_cmd_data); 177 } 178 179 /* 180 * i2c_wait_for_bb - Waits for bus busy 181 * 182 * Waits for bus busy 183 */ 184 static int i2c_wait_for_bb(void) 185 { 186 unsigned long start_time_bb = get_timer(0); 187 188 while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) || 189 !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) { 190 191 /* Evaluate timeout */ 192 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) 193 return 1; 194 } 195 196 return 0; 197 } 198 199 static int i2c_xfer_init(uchar chip, uint addr, int alen) 200 { 201 if (i2c_wait_for_bb()) 202 return 1; 203 204 i2c_setaddress(chip); 205 while (alen) { 206 alen--; 207 /* high byte address going out first */ 208 writel((addr >> (alen * 8)) & 0xff, 209 &i2c_regs_p->ic_cmd_data); 210 } 211 return 0; 212 } 213 214 static int i2c_xfer_finish(void) 215 { 216 ulong start_stop_det = get_timer(0); 217 218 while (1) { 219 if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) { 220 readl(&i2c_regs_p->ic_clr_stop_det); 221 break; 222 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { 223 break; 224 } 225 } 226 227 if (i2c_wait_for_bb()) { 228 printf("Timed out waiting for bus\n"); 229 return 1; 230 } 231 232 i2c_flush_rxfifo(); 233 234 return 0; 235 } 236 237 /* 238 * i2c_read - Read from i2c memory 239 * @chip: target i2c address 240 * @addr: address to read from 241 * @alen: 242 * @buffer: buffer for read data 243 * @len: no of bytes to be read 244 * 245 * Read from i2c memory. 246 */ 247 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 248 { 249 unsigned long start_time_rx; 250 251 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 252 /* 253 * EEPROM chips that implement "address overflow" are ones 254 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 255 * address and the extra bits end up in the "chip address" 256 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 257 * four 256 byte chips. 258 * 259 * Note that we consider the length of the address field to 260 * still be one byte because the extra address bits are 261 * hidden in the chip address. 262 */ 263 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 264 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 265 266 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, 267 addr); 268 #endif 269 270 if (i2c_xfer_init(chip, addr, alen)) 271 return 1; 272 273 start_time_rx = get_timer(0); 274 while (len) { 275 if (len == 1) 276 writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data); 277 else 278 writel(IC_CMD, &i2c_regs_p->ic_cmd_data); 279 280 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) { 281 *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data); 282 len--; 283 start_time_rx = get_timer(0); 284 285 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { 286 return 1; 287 } 288 } 289 290 return i2c_xfer_finish(); 291 } 292 293 /* 294 * i2c_write - Write to i2c memory 295 * @chip: target i2c address 296 * @addr: address to read from 297 * @alen: 298 * @buffer: buffer for read data 299 * @len: no of bytes to be read 300 * 301 * Write to i2c memory. 302 */ 303 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 304 { 305 int nb = len; 306 unsigned long start_time_tx; 307 308 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 309 /* 310 * EEPROM chips that implement "address overflow" are ones 311 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 312 * address and the extra bits end up in the "chip address" 313 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 314 * four 256 byte chips. 315 * 316 * Note that we consider the length of the address field to 317 * still be one byte because the extra address bits are 318 * hidden in the chip address. 319 */ 320 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 321 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 322 323 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, 324 addr); 325 #endif 326 327 if (i2c_xfer_init(chip, addr, alen)) 328 return 1; 329 330 start_time_tx = get_timer(0); 331 while (len) { 332 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) { 333 if (--len == 0) 334 writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data); 335 else 336 writel(*buffer, &i2c_regs_p->ic_cmd_data); 337 buffer++; 338 start_time_tx = get_timer(0); 339 340 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { 341 printf("Timed out. i2c write Failed\n"); 342 return 1; 343 } 344 } 345 346 return i2c_xfer_finish(); 347 } 348 349 /* 350 * i2c_probe - Probe the i2c chip 351 */ 352 int i2c_probe(uchar chip) 353 { 354 u32 tmp; 355 int ret; 356 357 /* 358 * Try to read the first location of the chip. 359 */ 360 ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); 361 if (ret) 362 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 363 364 return ret; 365 } 366 367 #ifdef CONFIG_I2C_MULTI_BUS 368 int i2c_set_bus_num(unsigned int bus) 369 { 370 switch (bus) { 371 case 0: 372 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE; 373 break; 374 #ifdef CONFIG_SYS_I2C_BASE1 375 case 1: 376 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1; 377 break; 378 #endif 379 #ifdef CONFIG_SYS_I2C_BASE2 380 case 2: 381 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2; 382 break; 383 #endif 384 #ifdef CONFIG_SYS_I2C_BASE3 385 case 3: 386 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3; 387 break; 388 #endif 389 #ifdef CONFIG_SYS_I2C_BASE4 390 case 4: 391 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4; 392 break; 393 #endif 394 #ifdef CONFIG_SYS_I2C_BASE5 395 case 5: 396 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5; 397 break; 398 #endif 399 #ifdef CONFIG_SYS_I2C_BASE6 400 case 6: 401 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6; 402 break; 403 #endif 404 #ifdef CONFIG_SYS_I2C_BASE7 405 case 7: 406 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7; 407 break; 408 #endif 409 #ifdef CONFIG_SYS_I2C_BASE8 410 case 8: 411 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8; 412 break; 413 #endif 414 #ifdef CONFIG_SYS_I2C_BASE9 415 case 9: 416 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9; 417 break; 418 #endif 419 default: 420 printf("Bad bus: %d\n", bus); 421 return -1; 422 } 423 424 current_bus = bus; 425 426 if (!bus_initialized[current_bus]) 427 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 428 429 return 0; 430 } 431 432 int i2c_get_bus_num(void) 433 { 434 return current_bus; 435 } 436 #endif 437