1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include "designware_i2c.h" 11 #include <i2c.h> 12 13 #ifdef CONFIG_I2C_MULTI_BUS 14 static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX]; 15 static unsigned int current_bus = 0; 16 #endif 17 18 static struct i2c_regs *i2c_regs_p = 19 (struct i2c_regs *)CONFIG_SYS_I2C_BASE; 20 21 /* 22 * set_speed - Set the i2c speed mode (standard, high, fast) 23 * @i2c_spd: required i2c speed mode 24 * 25 * Set the i2c speed mode (standard, high, fast) 26 */ 27 static void set_speed(int i2c_spd) 28 { 29 unsigned int cntl; 30 unsigned int hcnt, lcnt; 31 unsigned int enbl; 32 33 /* to set speed cltr must be disabled */ 34 enbl = readl(&i2c_regs_p->ic_enable); 35 enbl &= ~IC_ENABLE_0B; 36 writel(enbl, &i2c_regs_p->ic_enable); 37 38 cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK)); 39 40 switch (i2c_spd) { 41 case IC_SPEED_MODE_MAX: 42 cntl |= IC_CON_SPD_HS; 43 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; 44 writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt); 45 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; 46 writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt); 47 break; 48 49 case IC_SPEED_MODE_STANDARD: 50 cntl |= IC_CON_SPD_SS; 51 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; 52 writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt); 53 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; 54 writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt); 55 break; 56 57 case IC_SPEED_MODE_FAST: 58 default: 59 cntl |= IC_CON_SPD_FS; 60 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; 61 writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt); 62 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; 63 writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt); 64 break; 65 } 66 67 writel(cntl, &i2c_regs_p->ic_con); 68 69 /* Enable back i2c now speed set */ 70 enbl |= IC_ENABLE_0B; 71 writel(enbl, &i2c_regs_p->ic_enable); 72 } 73 74 /* 75 * i2c_set_bus_speed - Set the i2c speed 76 * @speed: required i2c speed 77 * 78 * Set the i2c speed. 79 */ 80 int i2c_set_bus_speed(unsigned int speed) 81 { 82 int i2c_spd; 83 84 if (speed >= I2C_MAX_SPEED) 85 i2c_spd = IC_SPEED_MODE_MAX; 86 else if (speed >= I2C_FAST_SPEED) 87 i2c_spd = IC_SPEED_MODE_FAST; 88 else 89 i2c_spd = IC_SPEED_MODE_STANDARD; 90 91 set_speed(i2c_spd); 92 93 return i2c_spd; 94 } 95 96 /* 97 * i2c_get_bus_speed - Gets the i2c speed 98 * 99 * Gets the i2c speed. 100 */ 101 unsigned int i2c_get_bus_speed(void) 102 { 103 u32 cntl; 104 105 cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK); 106 107 if (cntl == IC_CON_SPD_HS) 108 return I2C_MAX_SPEED; 109 else if (cntl == IC_CON_SPD_FS) 110 return I2C_FAST_SPEED; 111 else if (cntl == IC_CON_SPD_SS) 112 return I2C_STANDARD_SPEED; 113 114 return 0; 115 } 116 117 /* 118 * i2c_init - Init function 119 * @speed: required i2c speed 120 * @slaveadd: slave address for the device 121 * 122 * Initialization function. 123 */ 124 void i2c_init(int speed, int slaveadd) 125 { 126 unsigned int enbl; 127 128 /* Disable i2c */ 129 enbl = readl(&i2c_regs_p->ic_enable); 130 enbl &= ~IC_ENABLE_0B; 131 writel(enbl, &i2c_regs_p->ic_enable); 132 133 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con); 134 writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl); 135 writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl); 136 i2c_set_bus_speed(speed); 137 writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask); 138 writel(slaveadd, &i2c_regs_p->ic_sar); 139 140 /* Enable i2c */ 141 enbl = readl(&i2c_regs_p->ic_enable); 142 enbl |= IC_ENABLE_0B; 143 writel(enbl, &i2c_regs_p->ic_enable); 144 145 #ifdef CONFIG_I2C_MULTI_BUS 146 bus_initialized[current_bus] = 1; 147 #endif 148 } 149 150 /* 151 * i2c_setaddress - Sets the target slave address 152 * @i2c_addr: target i2c address 153 * 154 * Sets the target slave address. 155 */ 156 static void i2c_setaddress(unsigned int i2c_addr) 157 { 158 unsigned int enbl; 159 160 /* Disable i2c */ 161 enbl = readl(&i2c_regs_p->ic_enable); 162 enbl &= ~IC_ENABLE_0B; 163 writel(enbl, &i2c_regs_p->ic_enable); 164 165 writel(i2c_addr, &i2c_regs_p->ic_tar); 166 167 /* Enable i2c */ 168 enbl = readl(&i2c_regs_p->ic_enable); 169 enbl |= IC_ENABLE_0B; 170 writel(enbl, &i2c_regs_p->ic_enable); 171 } 172 173 /* 174 * i2c_flush_rxfifo - Flushes the i2c RX FIFO 175 * 176 * Flushes the i2c RX FIFO 177 */ 178 static void i2c_flush_rxfifo(void) 179 { 180 while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) 181 readl(&i2c_regs_p->ic_cmd_data); 182 } 183 184 /* 185 * i2c_wait_for_bb - Waits for bus busy 186 * 187 * Waits for bus busy 188 */ 189 static int i2c_wait_for_bb(void) 190 { 191 unsigned long start_time_bb = get_timer(0); 192 193 while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) || 194 !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) { 195 196 /* Evaluate timeout */ 197 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) 198 return 1; 199 } 200 201 return 0; 202 } 203 204 static int i2c_xfer_init(uchar chip, uint addr, int alen) 205 { 206 if (i2c_wait_for_bb()) 207 return 1; 208 209 i2c_setaddress(chip); 210 while (alen) { 211 alen--; 212 /* high byte address going out first */ 213 writel((addr >> (alen * 8)) & 0xff, 214 &i2c_regs_p->ic_cmd_data); 215 } 216 return 0; 217 } 218 219 static int i2c_xfer_finish(void) 220 { 221 ulong start_stop_det = get_timer(0); 222 223 while (1) { 224 if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) { 225 readl(&i2c_regs_p->ic_clr_stop_det); 226 break; 227 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { 228 break; 229 } 230 } 231 232 if (i2c_wait_for_bb()) { 233 printf("Timed out waiting for bus\n"); 234 return 1; 235 } 236 237 i2c_flush_rxfifo(); 238 239 return 0; 240 } 241 242 /* 243 * i2c_read - Read from i2c memory 244 * @chip: target i2c address 245 * @addr: address to read from 246 * @alen: 247 * @buffer: buffer for read data 248 * @len: no of bytes to be read 249 * 250 * Read from i2c memory. 251 */ 252 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 253 { 254 unsigned long start_time_rx; 255 256 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 257 /* 258 * EEPROM chips that implement "address overflow" are ones 259 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 260 * address and the extra bits end up in the "chip address" 261 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 262 * four 256 byte chips. 263 * 264 * Note that we consider the length of the address field to 265 * still be one byte because the extra address bits are 266 * hidden in the chip address. 267 */ 268 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 269 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 270 271 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, 272 addr); 273 #endif 274 275 if (i2c_xfer_init(chip, addr, alen)) 276 return 1; 277 278 start_time_rx = get_timer(0); 279 while (len) { 280 if (len == 1) 281 writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data); 282 else 283 writel(IC_CMD, &i2c_regs_p->ic_cmd_data); 284 285 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) { 286 *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data); 287 len--; 288 start_time_rx = get_timer(0); 289 290 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { 291 return 1; 292 } 293 } 294 295 return i2c_xfer_finish(); 296 } 297 298 /* 299 * i2c_write - Write to i2c memory 300 * @chip: target i2c address 301 * @addr: address to read from 302 * @alen: 303 * @buffer: buffer for read data 304 * @len: no of bytes to be read 305 * 306 * Write to i2c memory. 307 */ 308 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 309 { 310 int nb = len; 311 unsigned long start_time_tx; 312 313 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 314 /* 315 * EEPROM chips that implement "address overflow" are ones 316 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 317 * address and the extra bits end up in the "chip address" 318 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 319 * four 256 byte chips. 320 * 321 * Note that we consider the length of the address field to 322 * still be one byte because the extra address bits are 323 * hidden in the chip address. 324 */ 325 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 326 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 327 328 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, 329 addr); 330 #endif 331 332 if (i2c_xfer_init(chip, addr, alen)) 333 return 1; 334 335 start_time_tx = get_timer(0); 336 while (len) { 337 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) { 338 if (--len == 0) 339 writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data); 340 else 341 writel(*buffer, &i2c_regs_p->ic_cmd_data); 342 buffer++; 343 start_time_tx = get_timer(0); 344 345 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { 346 printf("Timed out. i2c write Failed\n"); 347 return 1; 348 } 349 } 350 351 return i2c_xfer_finish(); 352 } 353 354 /* 355 * i2c_probe - Probe the i2c chip 356 */ 357 int i2c_probe(uchar chip) 358 { 359 u32 tmp; 360 int ret; 361 362 /* 363 * Try to read the first location of the chip. 364 */ 365 ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); 366 if (ret) 367 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 368 369 return ret; 370 } 371 372 #ifdef CONFIG_I2C_MULTI_BUS 373 int i2c_set_bus_num(unsigned int bus) 374 { 375 switch (bus) { 376 case 0: 377 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE; 378 break; 379 #ifdef CONFIG_SYS_I2C_BASE1 380 case 1: 381 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1; 382 break; 383 #endif 384 #ifdef CONFIG_SYS_I2C_BASE2 385 case 2: 386 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2; 387 break; 388 #endif 389 #ifdef CONFIG_SYS_I2C_BASE3 390 case 3: 391 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3; 392 break; 393 #endif 394 #ifdef CONFIG_SYS_I2C_BASE4 395 case 4: 396 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4; 397 break; 398 #endif 399 #ifdef CONFIG_SYS_I2C_BASE5 400 case 5: 401 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5; 402 break; 403 #endif 404 #ifdef CONFIG_SYS_I2C_BASE6 405 case 6: 406 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6; 407 break; 408 #endif 409 #ifdef CONFIG_SYS_I2C_BASE7 410 case 7: 411 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7; 412 break; 413 #endif 414 #ifdef CONFIG_SYS_I2C_BASE8 415 case 8: 416 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8; 417 break; 418 #endif 419 #ifdef CONFIG_SYS_I2C_BASE9 420 case 9: 421 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9; 422 break; 423 #endif 424 default: 425 printf("Bad bus: %d\n", bus); 426 return -1; 427 } 428 429 current_bus = bus; 430 431 if (!bus_initialized[current_bus]) 432 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 433 434 return 0; 435 } 436 437 unsigned int i2c_get_bus_num(void) 438 { 439 return current_bus; 440 } 441 #endif 442