1 /* 2 * TI DaVinci (TMS320DM644x) I2C driver. 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> 7 * -------------------------------------------------------- 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 * 11 * NOTE: This driver should be converted to driver model before June 2017. 12 * Please see doc/driver-model/i2c-howto.txt for instructions. 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/i2c_defs.h> 19 #include <asm/io.h> 20 #include "davinci_i2c.h" 21 22 #define CHECK_NACK() \ 23 do {\ 24 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ 25 REG(&(i2c_base->i2c_con)) = 0;\ 26 return 1;\ 27 } \ 28 } while (0) 29 30 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap); 31 32 static int wait_for_bus(struct i2c_adapter *adap) 33 { 34 struct i2c_regs *i2c_base = davinci_get_base(adap); 35 int stat, timeout; 36 37 REG(&(i2c_base->i2c_stat)) = 0xffff; 38 39 for (timeout = 0; timeout < 10; timeout++) { 40 stat = REG(&(i2c_base->i2c_stat)); 41 if (!((stat) & I2C_STAT_BB)) { 42 REG(&(i2c_base->i2c_stat)) = 0xffff; 43 return 0; 44 } 45 46 REG(&(i2c_base->i2c_stat)) = stat; 47 udelay(50000); 48 } 49 50 REG(&(i2c_base->i2c_stat)) = 0xffff; 51 return 1; 52 } 53 54 55 static int poll_i2c_irq(struct i2c_adapter *adap, int mask) 56 { 57 struct i2c_regs *i2c_base = davinci_get_base(adap); 58 int stat, timeout; 59 60 for (timeout = 0; timeout < 10; timeout++) { 61 udelay(1000); 62 stat = REG(&(i2c_base->i2c_stat)); 63 if (stat & mask) 64 return stat; 65 } 66 67 REG(&(i2c_base->i2c_stat)) = 0xffff; 68 return stat | I2C_TIMEOUT; 69 } 70 71 static void flush_rx(struct i2c_adapter *adap) 72 { 73 struct i2c_regs *i2c_base = davinci_get_base(adap); 74 75 while (1) { 76 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) 77 break; 78 79 REG(&(i2c_base->i2c_drr)); 80 REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY; 81 udelay(1000); 82 } 83 } 84 85 static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed) 86 { 87 struct i2c_regs *i2c_base = davinci_get_base(adap); 88 uint32_t div, psc; 89 90 psc = 2; 91 /* SCLL + SCLH */ 92 div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; 93 REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ 94 REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ 95 REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); 96 97 adap->speed = speed; 98 return 0; 99 } 100 101 static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 102 { 103 struct i2c_regs *i2c_base = davinci_get_base(adap); 104 105 if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) { 106 REG(&(i2c_base->i2c_con)) = 0; 107 udelay(50000); 108 } 109 110 davinci_i2c_setspeed(adap, speed); 111 112 REG(&(i2c_base->i2c_oa)) = slaveadd; 113 REG(&(i2c_base->i2c_cnt)) = 0; 114 115 /* Interrupts must be enabled or I2C module won't work */ 116 REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | 117 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; 118 119 /* Now enable I2C controller (get it out of reset) */ 120 REG(&(i2c_base->i2c_con)) = I2C_CON_EN; 121 122 udelay(1000); 123 } 124 125 static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 126 { 127 struct i2c_regs *i2c_base = davinci_get_base(adap); 128 int rc = 1; 129 130 if (chip == REG(&(i2c_base->i2c_oa))) 131 return rc; 132 133 REG(&(i2c_base->i2c_con)) = 0; 134 if (wait_for_bus(adap)) 135 return 1; 136 137 /* try to read one byte from current (or only) address */ 138 REG(&(i2c_base->i2c_cnt)) = 1; 139 REG(&(i2c_base->i2c_sa)) = chip; 140 REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 141 I2C_CON_STP); 142 udelay(50000); 143 144 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) { 145 rc = 0; 146 flush_rx(adap); 147 REG(&(i2c_base->i2c_stat)) = 0xffff; 148 } else { 149 REG(&(i2c_base->i2c_stat)) = 0xffff; 150 REG(&(i2c_base->i2c_con)) |= I2C_CON_STP; 151 udelay(20000); 152 if (wait_for_bus(adap)) 153 return 1; 154 } 155 156 flush_rx(adap); 157 REG(&(i2c_base->i2c_stat)) = 0xffff; 158 REG(&(i2c_base->i2c_cnt)) = 0; 159 return rc; 160 } 161 162 static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip, 163 uint32_t addr, int alen, uint8_t *buf, int len) 164 { 165 struct i2c_regs *i2c_base = davinci_get_base(adap); 166 uint32_t tmp; 167 int i; 168 169 if ((alen < 0) || (alen > 2)) { 170 printf("%s(): bogus address length %x\n", __func__, alen); 171 return 1; 172 } 173 174 if (wait_for_bus(adap)) 175 return 1; 176 177 if (alen != 0) { 178 /* Start address phase */ 179 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; 180 REG(&(i2c_base->i2c_cnt)) = alen; 181 REG(&(i2c_base->i2c_sa)) = chip; 182 REG(&(i2c_base->i2c_con)) = tmp; 183 184 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); 185 186 CHECK_NACK(); 187 188 switch (alen) { 189 case 2: 190 /* Send address MSByte */ 191 if (tmp & I2C_STAT_XRDY) { 192 REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; 193 } else { 194 REG(&(i2c_base->i2c_con)) = 0; 195 return 1; 196 } 197 198 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); 199 200 CHECK_NACK(); 201 /* No break, fall through */ 202 case 1: 203 /* Send address LSByte */ 204 if (tmp & I2C_STAT_XRDY) { 205 REG(&(i2c_base->i2c_dxr)) = addr & 0xff; 206 } else { 207 REG(&(i2c_base->i2c_con)) = 0; 208 return 1; 209 } 210 211 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | 212 I2C_STAT_NACK | I2C_STAT_ARDY); 213 214 CHECK_NACK(); 215 216 if (!(tmp & I2C_STAT_ARDY)) { 217 REG(&(i2c_base->i2c_con)) = 0; 218 return 1; 219 } 220 } 221 } 222 223 /* Address phase is over, now read 'len' bytes and stop */ 224 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; 225 REG(&(i2c_base->i2c_cnt)) = len & 0xffff; 226 REG(&(i2c_base->i2c_sa)) = chip; 227 REG(&(i2c_base->i2c_con)) = tmp; 228 229 for (i = 0; i < len; i++) { 230 tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK | 231 I2C_STAT_ROVR); 232 233 CHECK_NACK(); 234 235 if (tmp & I2C_STAT_RRDY) { 236 buf[i] = REG(&(i2c_base->i2c_drr)); 237 } else { 238 REG(&(i2c_base->i2c_con)) = 0; 239 return 1; 240 } 241 } 242 243 tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); 244 245 CHECK_NACK(); 246 247 if (!(tmp & I2C_STAT_SCD)) { 248 REG(&(i2c_base->i2c_con)) = 0; 249 return 1; 250 } 251 252 flush_rx(adap); 253 REG(&(i2c_base->i2c_stat)) = 0xffff; 254 REG(&(i2c_base->i2c_cnt)) = 0; 255 REG(&(i2c_base->i2c_con)) = 0; 256 257 return 0; 258 } 259 260 static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip, 261 uint32_t addr, int alen, uint8_t *buf, int len) 262 { 263 struct i2c_regs *i2c_base = davinci_get_base(adap); 264 uint32_t tmp; 265 int i; 266 267 if ((alen < 0) || (alen > 2)) { 268 printf("%s(): bogus address length %x\n", __func__, alen); 269 return 1; 270 } 271 if (len < 0) { 272 printf("%s(): bogus length %x\n", __func__, len); 273 return 1; 274 } 275 276 if (wait_for_bus(adap)) 277 return 1; 278 279 /* Start address phase */ 280 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 281 I2C_CON_TRX | I2C_CON_STP; 282 REG(&(i2c_base->i2c_cnt)) = (alen == 0) ? 283 len & 0xffff : (len & 0xffff) + alen; 284 REG(&(i2c_base->i2c_sa)) = chip; 285 REG(&(i2c_base->i2c_con)) = tmp; 286 287 switch (alen) { 288 case 2: 289 /* Send address MSByte */ 290 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); 291 292 CHECK_NACK(); 293 294 if (tmp & I2C_STAT_XRDY) { 295 REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; 296 } else { 297 REG(&(i2c_base->i2c_con)) = 0; 298 return 1; 299 } 300 /* No break, fall through */ 301 case 1: 302 /* Send address LSByte */ 303 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); 304 305 CHECK_NACK(); 306 307 if (tmp & I2C_STAT_XRDY) { 308 REG(&(i2c_base->i2c_dxr)) = addr & 0xff; 309 } else { 310 REG(&(i2c_base->i2c_con)) = 0; 311 return 1; 312 } 313 } 314 315 for (i = 0; i < len; i++) { 316 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); 317 318 CHECK_NACK(); 319 320 if (tmp & I2C_STAT_XRDY) 321 REG(&(i2c_base->i2c_dxr)) = buf[i]; 322 else 323 return 1; 324 } 325 326 tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); 327 328 CHECK_NACK(); 329 330 if (!(tmp & I2C_STAT_SCD)) { 331 REG(&(i2c_base->i2c_con)) = 0; 332 return 1; 333 } 334 335 flush_rx(adap); 336 REG(&(i2c_base->i2c_stat)) = 0xffff; 337 REG(&(i2c_base->i2c_cnt)) = 0; 338 REG(&(i2c_base->i2c_con)) = 0; 339 340 return 0; 341 } 342 343 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap) 344 { 345 switch (adap->hwadapnr) { 346 #if I2C_BUS_MAX >= 3 347 case 2: 348 return (struct i2c_regs *)I2C2_BASE; 349 #endif 350 #if I2C_BUS_MAX >= 2 351 case 1: 352 return (struct i2c_regs *)I2C1_BASE; 353 #endif 354 case 0: 355 return (struct i2c_regs *)I2C_BASE; 356 357 default: 358 printf("wrong hwadapnr: %d\n", adap->hwadapnr); 359 } 360 361 return NULL; 362 } 363 364 U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe, 365 davinci_i2c_read, davinci_i2c_write, 366 davinci_i2c_setspeed, 367 CONFIG_SYS_DAVINCI_I2C_SPEED, 368 CONFIG_SYS_DAVINCI_I2C_SLAVE, 369 0) 370 371 #if I2C_BUS_MAX >= 2 372 U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe, 373 davinci_i2c_read, davinci_i2c_write, 374 davinci_i2c_setspeed, 375 CONFIG_SYS_DAVINCI_I2C_SPEED1, 376 CONFIG_SYS_DAVINCI_I2C_SLAVE1, 377 1) 378 #endif 379 380 #if I2C_BUS_MAX >= 3 381 U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe, 382 davinci_i2c_read, davinci_i2c_write, 383 davinci_i2c_setspeed, 384 CONFIG_SYS_DAVINCI_I2C_SPEED2, 385 CONFIG_SYS_DAVINCI_I2C_SLAVE2, 386 2) 387 #endif 388