xref: /openbmc/u-boot/drivers/i2c/Kconfig (revision dbb0696b) 
1#
2# I2C subsystem configuration
3#
4
5menu "I2C support"
6
7config DM_I2C
8	bool "Enable Driver Model for I2C drivers"
9	depends on DM
10	help
11	  Enable driver model for I2C. The I2C uclass interface: probe, read,
12	  write and speed, is implemented with the bus drivers operations,
13	  which provide methods for bus setting and data transfer. Each chip
14	  device (bus child) info is kept as parent platdata. The interface
15	  is defined in include/i2c.h. When i2c bus driver supports the i2c
16	  uclass, but the device drivers not, then DM_I2C_COMPAT config can
17	  be used as compatibility layer.
18
19config DM_I2C_COMPAT
20	bool "Enable I2C compatibility layer"
21	depends on DM
22	help
23	  Enable old-style I2C functions for compatibility with existing code.
24	  This option can be enabled as a temporary measure to avoid needing
25	  to convert all code for a board in a single commit. It should not
26	  be enabled for any board in an official release.
27
28config I2C_CROS_EC_TUNNEL
29	tristate "Chrome OS EC tunnel I2C bus"
30	depends on CROS_EC
31	help
32	  This provides an I2C bus that will tunnel i2c commands through to
33	  the other side of the Chrome OS EC to the I2C bus connected there.
34	  This will work whatever the interface used to talk to the EC (SPI,
35	  I2C or LPC). Some Chromebooks use this when the hardware design
36	  does not allow direct access to the main PMIC from the AP.
37
38config I2C_CROS_EC_LDO
39	bool "Provide access to LDOs on the Chrome OS EC"
40	depends on CROS_EC
41	---help---
42	On many Chromebooks the main PMIC is inaccessible to the AP. This is
43	often dealt with by using an I2C pass-through interface provided by
44	the EC. On some unfortunate models (e.g. Spring) the pass-through
45	is not available, and an LDO message is available instead. This
46	option enables a driver which provides very basic access to those
47	regulators, via the EC. We implement this as an I2C bus	which
48	emulates just the TPS65090 messages we know about. This is done to
49	avoid duplicating the logic in the TPS65090 regulator driver for
50	enabling/disabling an LDO.
51
52config I2C_SET_DEFAULT_BUS_NUM
53	bool "Set default I2C bus number"
54	depends on DM_I2C
55	help
56	  Set default number of I2C bus to be accessed. This option provides
57	  behaviour similar to old (i.e. pre DM) I2C bus driver.
58
59config I2C_DEFAULT_BUS_NUMBER
60	hex "I2C default bus number"
61	depends on I2C_SET_DEFAULT_BUS_NUM
62	default 0x0
63	help
64	  Number of default I2C bus to use
65
66config DM_I2C_GPIO
67	bool "Enable Driver Model for software emulated I2C bus driver"
68	depends on DM_I2C && DM_GPIO
69	help
70	  Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
71	  configuration is given by the device tree. Kernel-style device tree
72	  bindings are supported.
73	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
74
75config SYS_I2C_AT91
76	bool "Atmel I2C driver"
77	depends on DM_I2C && ARCH_AT91
78	help
79	  Add support for the Atmel I2C driver. A serious problem is that there
80	  is no documented way to issue repeated START conditions for more than
81	  two messages, as needed to support combined I2C messages. Use the
82	  i2c-gpio driver unless your system can cope with this limitation.
83	  Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
84
85config SYS_I2C_FSL
86       bool "Freescale I2C bus driver"
87       depends on DM_I2C
88       help
89	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
90	  MPC85xx processors.
91
92config SYS_I2C_CADENCE
93	tristate "Cadence I2C Controller"
94	depends on DM_I2C && (ARCH_ZYNQ || ARM64)
95	help
96	  Say yes here to select Cadence I2C Host Controller. This controller is
97	  e.g. used by Xilinx Zynq.
98
99config SYS_I2C_DAVINCI
100	bool "Davinci I2C Controller"
101	depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
102	help
103	  Say yes here to add support for Davinci and Keystone I2C controller
104
105config SYS_I2C_DW
106	bool "Designware I2C Controller"
107	default n
108	help
109	  Say yes here to select the Designware I2C Host Controller. This
110	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
111	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
112
113config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
114	bool "DW I2C Enable Status Register not supported"
115	depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
116		TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
117	default y
118	help
119	  Some versions of the Designware I2C controller do not support the
120	  enable status register. This config option can be enabled in such
121	  cases.
122
123config SYS_I2C_ASPEED
124	bool "Aspeed I2C Controller"
125	depends on DM_I2C && ARCH_ASPEED
126	help
127	  Say yes here to select Aspeed I2C Host Controller. The driver
128	  supports AST2500 and AST2400 controllers, but is very limited.
129	  Only single master mode is supported and only byte-by-byte
130	  synchronous reads and writes are supported, no Pool Buffers or DMA.
131
132config SYS_I2C_INTEL
133	bool "Intel I2C/SMBUS driver"
134	depends on DM_I2C
135	help
136	  Add support for the Intel SMBUS driver. So far this driver is just
137	  a stub which perhaps some basic init. There is no implementation of
138	  the I2C API meaning that any I2C operations will immediately fail
139	  for now.
140
141config SYS_I2C_IMX_LPI2C
142	bool "NXP i.MX LPI2C driver"
143	help
144	  Add support for the NXP i.MX LPI2C driver.
145
146config SYS_I2C_MESON
147	bool "Amlogic Meson I2C driver"
148	depends on DM_I2C && ARCH_MESON
149	help
150	  Add support for the I2C controller available in Amlogic Meson
151	  SoCs. The controller supports programmable bus speed including
152	  standard (100kbits/s) and fast (400kbit/s) speed and allows the
153	  software to define a flexible format of the bit streams. It has an
154	  internal buffer holding up to 8 bytes for transfers and supports
155	  both 7-bit and 10-bit addresses.
156
157config SYS_I2C_MXC
158	bool "NXP MXC I2C driver"
159	help
160	  Add support for the NXP I2C driver. This supports up to four bus
161	  channels and operating on standard mode up to 100 kbits/s and fast
162	  mode up to 400 kbits/s.
163
164if SYS_I2C_MXC
165config SYS_I2C_MXC_I2C1
166	bool "NXP MXC I2C1"
167	help
168	 Add support for NXP MXC I2C Controller 1.
169	 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
170
171config SYS_I2C_MXC_I2C2
172	bool "NXP MXC I2C2"
173	help
174	 Add support for NXP MXC I2C Controller 2.
175	 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
176
177config SYS_I2C_MXC_I2C3
178	bool "NXP MXC I2C3"
179	help
180	 Add support for NXP MXC I2C Controller 3.
181	 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
182
183config SYS_I2C_MXC_I2C4
184	bool "NXP MXC I2C4"
185	help
186	 Add support for NXP MXC I2C Controller 4.
187	 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
188
189config SYS_I2C_MXC_I2C5
190	bool "NXP MXC I2C5"
191	help
192	 Add support for NXP MXC I2C Controller 5.
193	 Required for SoCs which have I2C MXC controller 5 eg LX2160A
194
195config SYS_I2C_MXC_I2C6
196	bool "NXP MXC I2C6"
197	help
198	 Add support for NXP MXC I2C Controller 6.
199	 Required for SoCs which have I2C MXC controller 6 eg LX2160A
200
201config SYS_I2C_MXC_I2C7
202	bool "NXP MXC I2C7"
203	help
204	 Add support for NXP MXC I2C Controller 7.
205	 Required for SoCs which have I2C MXC controller 7 eg LX2160A
206
207config SYS_I2C_MXC_I2C8
208	bool "NXP MXC I2C8"
209	help
210	 Add support for NXP MXC I2C Controller 8.
211	 Required for SoCs which have I2C MXC controller 8 eg LX2160A
212endif
213
214if SYS_I2C_MXC_I2C1
215config SYS_MXC_I2C1_SPEED
216	int "I2C Channel 1 speed"
217	default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
218	default 100000
219	help
220	 MXC I2C Channel 1 speed
221
222config SYS_MXC_I2C1_SLAVE
223	int "I2C1 Slave"
224	default 0
225	help
226	 MXC I2C1 Slave
227endif
228
229if SYS_I2C_MXC_I2C2
230config SYS_MXC_I2C2_SPEED
231	int "I2C Channel 2 speed"
232	default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
233	default 100000
234	help
235	 MXC I2C Channel 2 speed
236
237config SYS_MXC_I2C2_SLAVE
238	int "I2C2 Slave"
239	default 0
240	help
241	 MXC I2C2 Slave
242endif
243
244if SYS_I2C_MXC_I2C3
245config SYS_MXC_I2C3_SPEED
246	int "I2C Channel 3 speed"
247	default 100000
248	help
249	 MXC I2C Channel 3 speed
250
251config SYS_MXC_I2C3_SLAVE
252	int "I2C3 Slave"
253	default 0
254	help
255	 MXC I2C3 Slave
256endif
257
258if SYS_I2C_MXC_I2C4
259config SYS_MXC_I2C4_SPEED
260	int "I2C Channel 4 speed"
261	default 100000
262	help
263	 MXC I2C Channel 4 speed
264
265config SYS_MXC_I2C4_SLAVE
266	int "I2C4 Slave"
267	default 0
268	help
269	 MXC I2C4 Slave
270endif
271
272if SYS_I2C_MXC_I2C5
273config SYS_MXC_I2C5_SPEED
274	int "I2C Channel 5 speed"
275	default 100000
276	help
277	 MXC I2C Channel 5 speed
278
279config SYS_MXC_I2C5_SLAVE
280	int "I2C5 Slave"
281	default 0
282	help
283	 MXC I2C5 Slave
284endif
285
286if SYS_I2C_MXC_I2C6
287config SYS_MXC_I2C6_SPEED
288	int "I2C Channel 6 speed"
289	default 100000
290	help
291	 MXC I2C Channel 6 speed
292
293config SYS_MXC_I2C6_SLAVE
294	int "I2C6 Slave"
295	default 0
296	help
297	 MXC I2C6 Slave
298endif
299
300if SYS_I2C_MXC_I2C7
301config SYS_MXC_I2C7_SPEED
302	int "I2C Channel 7 speed"
303	default 100000
304	help
305	 MXC I2C Channel 7 speed
306
307config SYS_MXC_I2C7_SLAVE
308	int "I2C7 Slave"
309	default 0
310	help
311	 MXC I2C7 Slave
312endif
313
314if SYS_I2C_MXC_I2C8
315config SYS_MXC_I2C8_SPEED
316	int "I2C Channel 8 speed"
317	default 100000
318	help
319	 MXC I2C Channel 8 speed
320
321config SYS_MXC_I2C8_SLAVE
322	int "I2C8 Slave"
323	default 0
324	help
325	 MXC I2C8 Slave
326endif
327
328config SYS_I2C_OMAP24XX
329	bool "TI OMAP2+ I2C driver"
330	depends on ARCH_OMAP2PLUS
331	help
332	  Add support for the OMAP2+ I2C driver.
333
334if SYS_I2C_OMAP24XX
335config SYS_OMAP24_I2C_SLAVE
336	int "I2C Slave addr channel 0"
337	default 1
338	help
339	  OMAP24xx I2C Slave address channel 0
340
341config SYS_OMAP24_I2C_SPEED
342	int "I2C Slave channel 0 speed"
343	default 100000
344	help
345	  OMAP24xx Slave speed channel 0
346endif
347
348config SYS_I2C_RCAR_I2C
349	bool "Renesas RCar I2C driver"
350	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
351	help
352	  Support for Renesas RCar I2C controller.
353
354config SYS_I2C_RCAR_IIC
355	bool "Renesas RCar Gen3 IIC driver"
356	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
357	help
358	  Support for Renesas RCar Gen3 IIC controller.
359
360config SYS_I2C_ROCKCHIP
361	bool "Rockchip I2C driver"
362	depends on DM_I2C
363	help
364	  Add support for the Rockchip I2C driver. This is used with various
365	  Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
366	  have several I2C ports and all are provided, controlled by the
367	  device tree.
368
369config SYS_I2C_SANDBOX
370	bool "Sandbox I2C driver"
371	depends on SANDBOX && DM_I2C
372	help
373	  Enable I2C support for sandbox. This is an emulation of a real I2C
374	  bus. Devices can be attached to the bus using the device tree
375	  which specifies the driver to use.  See sandbox.dts as an example.
376
377config SYS_I2C_S3C24X0
378	bool "Samsung I2C driver"
379	depends on ARCH_EXYNOS4 && DM_I2C
380	help
381	  Support for Samsung I2C controller as Samsung SoCs.
382
383config SYS_I2C_STM32F7
384	bool "STMicroelectronics STM32F7 I2C support"
385	depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
386	help
387	  Enable this option to add support for STM32 I2C controller
388	  introduced with STM32F7/H7 SoCs. This I2C controller supports :
389	   _ Slave and master modes
390	   _ Multimaster capability
391	   _ Standard-mode (up to 100 kHz)
392	   _ Fast-mode (up to 400 kHz)
393	   _ Fast-mode Plus (up to 1 MHz)
394	   _ 7-bit and 10-bit addressing mode
395	   _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
396	   _ All 7-bit addresses acknowledge mode
397	   _ General call
398	   _ Programmable setup and hold times
399	   _ Easy to use event management
400	   _ Optional clock stretching
401	   _ Software reset
402
403config SYS_I2C_UNIPHIER
404	bool "UniPhier I2C driver"
405	depends on ARCH_UNIPHIER && DM_I2C
406	default y
407	help
408	  Support for UniPhier I2C controller driver.  This I2C controller
409	  is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
410
411config SYS_I2C_UNIPHIER_F
412	bool "UniPhier FIFO-builtin I2C driver"
413	depends on ARCH_UNIPHIER && DM_I2C
414	default y
415	help
416	  Support for UniPhier FIFO-builtin I2C controller driver.
417	  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
418
419config SYS_I2C_VERSATILE
420	bool "Arm Ltd Versatile I2C bus driver"
421	depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO)
422	help
423	  Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
424	  controller is present in the development boards manufactured by Arm Ltd.
425
426config SYS_I2C_MVTWSI
427	bool "Marvell I2C driver"
428	depends on DM_I2C
429	help
430	  Support for Marvell I2C controllers as used on the orion5x and
431	  kirkwood SoC families.
432
433config TEGRA186_BPMP_I2C
434	bool "Enable Tegra186 BPMP-based I2C driver"
435	depends on TEGRA186_BPMP
436	help
437	  Support for Tegra I2C controllers managed by the BPMP (Boot and
438	  Power Management Processor). On Tegra186, some I2C controllers are
439	  directly controlled by the main CPU, whereas others are controlled
440	  by the BPMP, and can only be accessed by the main CPU via IPC
441	  requests to the BPMP. This driver covers the latter case.
442
443config SYS_I2C_BUS_MAX
444	int "Max I2C busses"
445	depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
446	default 2 if TI816X
447	default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
448	default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
449	default 5 if OMAP54XX
450	help
451	  Define the maximum number of available I2C buses.
452
453config SYS_I2C_XILINX_XIIC
454	bool "Xilinx AXI I2C driver"
455	depends on DM_I2C
456	help
457	  Support for Xilinx AXI I2C controller.
458
459config SYS_I2C_ZYNQ
460	bool "Xilinx I2C driver"
461	depends on ARCH_ZYNQMP || ARCH_ZYNQ
462	depends on !DM_I2C
463	help
464	  Support for Xilinx I2C controller.
465
466config SYS_I2C_ZYNQ_SLAVE
467	hex "Set slave addr"
468	depends on SYS_I2C_ZYNQ
469	default 0
470	help
471	  Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr.
472
473config SYS_I2C_ZYNQ_SPEED
474	int "Set I2C speed"
475	depends on SYS_I2C_ZYNQ
476	default 100000
477	help
478	  Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting.
479
480config ZYNQ_I2C0
481	bool "Xilinx I2C0 controller"
482	depends on SYS_I2C_ZYNQ
483	help
484	  Enable Xilinx I2C0 controller.
485
486config ZYNQ_I2C1
487	bool "Xilinx I2C1 controller"
488	depends on SYS_I2C_ZYNQ
489	help
490	  Enable Xilinx I2C1 controller.
491
492config SYS_I2C_IHS
493        bool "gdsys IHS I2C driver"
494        depends on DM_I2C
495        help
496          Support for gdsys IHS I2C driver on FPGA bus.
497
498source "drivers/i2c/muxes/Kconfig"
499
500endmenu
501