1# 2# I2C subsystem configuration 3# 4 5menu "I2C support" 6 7config DM_I2C 8 bool "Enable Driver Model for I2C drivers" 9 depends on DM 10 help 11 Enable driver model for I2C. The I2C uclass interface: probe, read, 12 write and speed, is implemented with the bus drivers operations, 13 which provide methods for bus setting and data transfer. Each chip 14 device (bus child) info is kept as parent platdata. The interface 15 is defined in include/i2c.h. When i2c bus driver supports the i2c 16 uclass, but the device drivers not, then DM_I2C_COMPAT config can 17 be used as compatibility layer. 18 19config DM_I2C_COMPAT 20 bool "Enable I2C compatibility layer" 21 depends on DM 22 help 23 Enable old-style I2C functions for compatibility with existing code. 24 This option can be enabled as a temporary measure to avoid needing 25 to convert all code for a board in a single commit. It should not 26 be enabled for any board in an official release. 27 28config I2C_CROS_EC_TUNNEL 29 tristate "Chrome OS EC tunnel I2C bus" 30 depends on CROS_EC 31 help 32 This provides an I2C bus that will tunnel i2c commands through to 33 the other side of the Chrome OS EC to the I2C bus connected there. 34 This will work whatever the interface used to talk to the EC (SPI, 35 I2C or LPC). Some Chromebooks use this when the hardware design 36 does not allow direct access to the main PMIC from the AP. 37 38config I2C_CROS_EC_LDO 39 bool "Provide access to LDOs on the Chrome OS EC" 40 depends on CROS_EC 41 ---help--- 42 On many Chromebooks the main PMIC is inaccessible to the AP. This is 43 often dealt with by using an I2C pass-through interface provided by 44 the EC. On some unfortunate models (e.g. Spring) the pass-through 45 is not available, and an LDO message is available instead. This 46 option enables a driver which provides very basic access to those 47 regulators, via the EC. We implement this as an I2C bus which 48 emulates just the TPS65090 messages we know about. This is done to 49 avoid duplicating the logic in the TPS65090 regulator driver for 50 enabling/disabling an LDO. 51 52config DM_I2C_GPIO 53 bool "Enable Driver Model for software emulated I2C bus driver" 54 depends on DM_I2C && DM_GPIO 55 help 56 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO 57 configuration is given by the device tree. Kernel-style device tree 58 bindings are supported. 59 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt 60 61config SYS_I2C_SANDBOX 62 bool "Sandbox I2C driver" 63 depends on SANDBOX && DM_I2C 64 help 65 Enable I2C support for sandbox. This is an emulation of a real I2C 66 bus. Devices can be attached to the bus using the device tree 67 which specifies the driver to use. As an example, see this device 68 tree fragment from sandbox.dts. It shows that the I2C bus has a 69 single EEPROM at address 0x2c (7-bit address) which is emulated by 70 the driver for "sandbox,i2c-eeprom", which is in 71 drivers/misc/i2c_eeprom_emul.c. 72 73 i2c@0 { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 reg = <0>; 77 compatible = "sandbox,i2c"; 78 clock-frequency = <400000>; 79 eeprom@2c { 80 reg = <0x2c>; 81 compatible = "i2c-eeprom"; 82 emul { 83 compatible = "sandbox,i2c-eeprom"; 84 sandbox,filename = "i2c.bin"; 85 sandbox,size = <128>; 86 }; 87 }; 88 }; 89 90 91config SYS_I2C_UNIPHIER 92 bool "UniPhier I2C driver" 93 depends on ARCH_UNIPHIER && DM_I2C 94 default y 95 help 96 Support for UniPhier I2C controller driver. This I2C controller 97 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. 98 99config SYS_I2C_UNIPHIER_F 100 bool "UniPhier FIFO-builtin I2C driver" 101 depends on ARCH_UNIPHIER && DM_I2C 102 default y 103 help 104 Support for UniPhier FIFO-builtin I2C controller driver. 105 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. 106 107source "drivers/i2c/muxes/Kconfig" 108 109endmenu 110