1 /* 2 * Xilinx Zynq GPIO device driver 3 * 4 * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu> 5 * 6 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c) 7 * Copyright (C) 2009 - 2014 Xilinx, Inc. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/gpio.h> 14 #include <asm/io.h> 15 #include <linux/errno.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 /* Maximum banks */ 22 #define ZYNQ_GPIO_MAX_BANK 4 23 24 #define ZYNQ_GPIO_BANK0_NGPIO 32 25 #define ZYNQ_GPIO_BANK1_NGPIO 22 26 #define ZYNQ_GPIO_BANK2_NGPIO 32 27 #define ZYNQ_GPIO_BANK3_NGPIO 32 28 29 #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ 30 ZYNQ_GPIO_BANK1_NGPIO + \ 31 ZYNQ_GPIO_BANK2_NGPIO + \ 32 ZYNQ_GPIO_BANK3_NGPIO) 33 34 #define ZYNQMP_GPIO_MAX_BANK 6 35 36 #define ZYNQMP_GPIO_BANK0_NGPIO 26 37 #define ZYNQMP_GPIO_BANK1_NGPIO 26 38 #define ZYNQMP_GPIO_BANK2_NGPIO 26 39 #define ZYNQMP_GPIO_BANK3_NGPIO 32 40 #define ZYNQMP_GPIO_BANK4_NGPIO 32 41 #define ZYNQMP_GPIO_BANK5_NGPIO 32 42 43 #define ZYNQMP_GPIO_NR_GPIOS 174 44 45 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 46 #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ 47 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 48 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) 49 #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ 50 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 51 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) 52 #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ 53 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 54 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) 55 #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ 56 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 57 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) 58 #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ 59 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 60 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) 61 #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 62 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 63 64 /* Register offsets for the GPIO device */ 65 /* LSW Mask & Data -WO */ 66 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) 67 /* MSW Mask & Data -WO */ 68 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) 69 /* Data Register-RW */ 70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) 71 /* Direction mode reg-RW */ 72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) 73 /* Output enable reg-RW */ 74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) 75 /* Interrupt mask reg-RO */ 76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) 77 /* Interrupt enable reg-WO */ 78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) 79 /* Interrupt disable reg-WO */ 80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) 81 /* Interrupt status reg-RO */ 82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) 83 /* Interrupt type reg-RW */ 84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) 85 /* Interrupt polarity reg-RW */ 86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) 87 /* Interrupt on any, reg-RW */ 88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) 89 90 /* Disable all interrupts mask */ 91 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF 92 93 /* Mid pin number of a bank */ 94 #define ZYNQ_GPIO_MID_PIN_NUM 16 95 96 /* GPIO upper 16 bit mask */ 97 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 98 99 struct zynq_gpio_privdata { 100 phys_addr_t base; 101 const struct zynq_platform_data *p_data; 102 }; 103 104 /** 105 * struct zynq_platform_data - zynq gpio platform data structure 106 * @label: string to store in gpio->label 107 * @ngpio: max number of gpio pins 108 * @max_bank: maximum number of gpio banks 109 * @bank_min: this array represents bank's min pin 110 * @bank_max: this array represents bank's max pin 111 */ 112 struct zynq_platform_data { 113 const char *label; 114 u16 ngpio; 115 int max_bank; 116 int bank_min[ZYNQMP_GPIO_MAX_BANK]; 117 int bank_max[ZYNQMP_GPIO_MAX_BANK]; 118 }; 119 120 static const struct zynq_platform_data zynqmp_gpio_def = { 121 .label = "zynqmp_gpio", 122 .ngpio = ZYNQMP_GPIO_NR_GPIOS, 123 .max_bank = ZYNQMP_GPIO_MAX_BANK, 124 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 125 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), 126 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), 127 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), 128 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), 129 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), 130 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), 131 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), 132 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), 133 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), 134 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), 135 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), 136 }; 137 138 static const struct zynq_platform_data zynq_gpio_def = { 139 .label = "zynq_gpio", 140 .ngpio = ZYNQ_GPIO_NR_GPIOS, 141 .max_bank = ZYNQ_GPIO_MAX_BANK, 142 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 143 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), 144 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), 145 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), 146 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), 147 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), 148 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), 149 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), 150 }; 151 152 /** 153 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank 154 * for a given pin in the GPIO device 155 * @pin_num: gpio pin number within the device 156 * @bank_num: an output parameter used to return the bank number of the gpio 157 * pin 158 * @bank_pin_num: an output parameter used to return pin number within a bank 159 * for the given gpio pin 160 * 161 * Returns the bank number and pin offset within the bank. 162 */ 163 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, 164 unsigned int *bank_num, 165 unsigned int *bank_pin_num, 166 struct udevice *dev) 167 { 168 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 169 int bank; 170 171 for (bank = 0; bank < priv->p_data->max_bank; bank++) { 172 if ((pin_num >= priv->p_data->bank_min[bank]) && 173 (pin_num <= priv->p_data->bank_max[bank])) { 174 *bank_num = bank; 175 *bank_pin_num = pin_num - 176 priv->p_data->bank_min[bank]; 177 return; 178 } 179 } 180 181 if (bank >= priv->p_data->max_bank) { 182 printf("Inavlid bank and pin num\n"); 183 *bank_num = 0; 184 *bank_pin_num = 0; 185 } 186 } 187 188 static int gpio_is_valid(unsigned gpio, struct udevice *dev) 189 { 190 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 191 192 return (gpio >= 0) && (gpio < priv->p_data->ngpio); 193 } 194 195 static int check_gpio(unsigned gpio, struct udevice *dev) 196 { 197 if (!gpio_is_valid(gpio, dev)) { 198 printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); 199 return -1; 200 } 201 return 0; 202 } 203 204 static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) 205 { 206 u32 data; 207 unsigned int bank_num, bank_pin_num; 208 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 209 210 if (check_gpio(gpio, dev) < 0) 211 return -1; 212 213 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 214 215 data = readl(priv->base + 216 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 217 218 return (data >> bank_pin_num) & 1; 219 } 220 221 static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) 222 { 223 unsigned int reg_offset, bank_num, bank_pin_num; 224 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 225 226 if (check_gpio(gpio, dev) < 0) 227 return -1; 228 229 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 230 231 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { 232 /* only 16 data bits in bit maskable reg */ 233 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; 234 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); 235 } else { 236 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); 237 } 238 239 /* 240 * get the 32 bit value to be written to the mask/data register where 241 * the upper 16 bits is the mask and lower 16 bits is the data 242 */ 243 value = !!value; 244 value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & 245 ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); 246 247 writel(value, priv->base + reg_offset); 248 249 return 0; 250 } 251 252 static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) 253 { 254 u32 reg; 255 unsigned int bank_num, bank_pin_num; 256 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 257 258 if (check_gpio(gpio, dev) < 0) 259 return -1; 260 261 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 262 263 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ 264 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) 265 return -1; 266 267 /* clear the bit in direction mode reg to set the pin as input */ 268 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 269 reg &= ~BIT(bank_pin_num); 270 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 271 272 return 0; 273 } 274 275 static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, 276 int value) 277 { 278 u32 reg; 279 unsigned int bank_num, bank_pin_num; 280 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 281 282 if (check_gpio(gpio, dev) < 0) 283 return -1; 284 285 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 286 287 /* set the GPIO pin as output */ 288 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 289 reg |= BIT(bank_pin_num); 290 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 291 292 /* configure the output enable reg for the pin */ 293 reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 294 reg |= BIT(bank_pin_num); 295 writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 296 297 /* set the state of the pin */ 298 gpio_set_value(gpio, value); 299 return 0; 300 } 301 302 static int zynq_gpio_get_function(struct udevice *dev, unsigned offset) 303 { 304 u32 reg; 305 unsigned int bank_num, bank_pin_num; 306 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 307 308 if (check_gpio(offset, dev) < 0) 309 return -1; 310 311 zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev); 312 313 /* set the GPIO pin as output */ 314 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 315 reg &= BIT(bank_pin_num); 316 if (reg) 317 return GPIOF_OUTPUT; 318 else 319 return GPIOF_INPUT; 320 } 321 322 static const struct dm_gpio_ops gpio_zynq_ops = { 323 .direction_input = zynq_gpio_direction_input, 324 .direction_output = zynq_gpio_direction_output, 325 .get_value = zynq_gpio_get_value, 326 .set_value = zynq_gpio_set_value, 327 .get_function = zynq_gpio_get_function, 328 }; 329 330 static const struct udevice_id zynq_gpio_ids[] = { 331 { .compatible = "xlnx,zynq-gpio-1.0", 332 .data = (ulong)&zynq_gpio_def}, 333 { .compatible = "xlnx,zynqmp-gpio-1.0", 334 .data = (ulong)&zynqmp_gpio_def}, 335 { } 336 }; 337 338 static void zynq_gpio_getplat_data(struct udevice *dev) 339 { 340 const struct udevice_id *of_match = zynq_gpio_ids; 341 int ret; 342 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 343 344 while (of_match->compatible) { 345 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 346 of_match->compatible); 347 if (ret >= 0) { 348 priv->p_data = 349 (struct zynq_platform_data *)of_match->data; 350 break; 351 } else { 352 of_match++; 353 continue; 354 } 355 } 356 357 if (!priv->p_data) 358 printf("No Platform data found\n"); 359 } 360 361 static int zynq_gpio_probe(struct udevice *dev) 362 { 363 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 364 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 365 366 zynq_gpio_getplat_data(dev); 367 368 if (priv->p_data) 369 uc_priv->gpio_count = priv->p_data->ngpio; 370 371 return 0; 372 } 373 374 static int zynq_gpio_ofdata_to_platdata(struct udevice *dev) 375 { 376 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 377 378 priv->base = devfdt_get_addr(dev); 379 380 return 0; 381 } 382 383 U_BOOT_DRIVER(gpio_zynq) = { 384 .name = "gpio_zynq", 385 .id = UCLASS_GPIO, 386 .ops = &gpio_zynq_ops, 387 .of_match = zynq_gpio_ids, 388 .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata, 389 .probe = zynq_gpio_probe, 390 .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata), 391 }; 392