1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Xilinx Zynq GPIO device driver 4 * 5 * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu> 6 * 7 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c) 8 * Copyright (C) 2009 - 2014 Xilinx, Inc. 9 */ 10 11 #include <common.h> 12 #include <asm/gpio.h> 13 #include <asm/io.h> 14 #include <linux/errno.h> 15 #include <dm.h> 16 #include <fdtdec.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* Maximum banks */ 21 #define ZYNQ_GPIO_MAX_BANK 4 22 23 #define ZYNQ_GPIO_BANK0_NGPIO 32 24 #define ZYNQ_GPIO_BANK1_NGPIO 22 25 #define ZYNQ_GPIO_BANK2_NGPIO 32 26 #define ZYNQ_GPIO_BANK3_NGPIO 32 27 28 #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ 29 ZYNQ_GPIO_BANK1_NGPIO + \ 30 ZYNQ_GPIO_BANK2_NGPIO + \ 31 ZYNQ_GPIO_BANK3_NGPIO) 32 33 #define ZYNQMP_GPIO_MAX_BANK 6 34 35 #define ZYNQMP_GPIO_BANK0_NGPIO 26 36 #define ZYNQMP_GPIO_BANK1_NGPIO 26 37 #define ZYNQMP_GPIO_BANK2_NGPIO 26 38 #define ZYNQMP_GPIO_BANK3_NGPIO 32 39 #define ZYNQMP_GPIO_BANK4_NGPIO 32 40 #define ZYNQMP_GPIO_BANK5_NGPIO 32 41 42 #define ZYNQMP_GPIO_NR_GPIOS 174 43 44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 45 #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ 46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) 48 #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ 49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) 51 #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ 52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 53 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) 54 #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ 55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 56 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) 57 #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ 58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 59 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) 60 #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 62 63 /* Register offsets for the GPIO device */ 64 /* LSW Mask & Data -WO */ 65 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) 66 /* MSW Mask & Data -WO */ 67 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) 68 /* Data Register-RW */ 69 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) 70 /* Direction mode reg-RW */ 71 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) 72 /* Output enable reg-RW */ 73 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) 74 /* Interrupt mask reg-RO */ 75 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) 76 /* Interrupt enable reg-WO */ 77 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) 78 /* Interrupt disable reg-WO */ 79 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) 80 /* Interrupt status reg-RO */ 81 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) 82 /* Interrupt type reg-RW */ 83 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) 84 /* Interrupt polarity reg-RW */ 85 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) 86 /* Interrupt on any, reg-RW */ 87 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) 88 89 /* Disable all interrupts mask */ 90 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF 91 92 /* Mid pin number of a bank */ 93 #define ZYNQ_GPIO_MID_PIN_NUM 16 94 95 /* GPIO upper 16 bit mask */ 96 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 97 98 struct zynq_gpio_privdata { 99 phys_addr_t base; 100 const struct zynq_platform_data *p_data; 101 }; 102 103 /** 104 * struct zynq_platform_data - zynq gpio platform data structure 105 * @label: string to store in gpio->label 106 * @ngpio: max number of gpio pins 107 * @max_bank: maximum number of gpio banks 108 * @bank_min: this array represents bank's min pin 109 * @bank_max: this array represents bank's max pin 110 */ 111 struct zynq_platform_data { 112 const char *label; 113 u16 ngpio; 114 int max_bank; 115 int bank_min[ZYNQMP_GPIO_MAX_BANK]; 116 int bank_max[ZYNQMP_GPIO_MAX_BANK]; 117 }; 118 119 static const struct zynq_platform_data zynqmp_gpio_def = { 120 .label = "zynqmp_gpio", 121 .ngpio = ZYNQMP_GPIO_NR_GPIOS, 122 .max_bank = ZYNQMP_GPIO_MAX_BANK, 123 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 124 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), 125 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), 126 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), 127 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), 128 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), 129 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), 130 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), 131 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), 132 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), 133 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), 134 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), 135 }; 136 137 static const struct zynq_platform_data zynq_gpio_def = { 138 .label = "zynq_gpio", 139 .ngpio = ZYNQ_GPIO_NR_GPIOS, 140 .max_bank = ZYNQ_GPIO_MAX_BANK, 141 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 142 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), 143 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), 144 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), 145 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), 146 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), 147 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), 148 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), 149 }; 150 151 /** 152 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank 153 * for a given pin in the GPIO device 154 * @pin_num: gpio pin number within the device 155 * @bank_num: an output parameter used to return the bank number of the gpio 156 * pin 157 * @bank_pin_num: an output parameter used to return pin number within a bank 158 * for the given gpio pin 159 * 160 * Returns the bank number and pin offset within the bank. 161 */ 162 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, 163 unsigned int *bank_num, 164 unsigned int *bank_pin_num, 165 struct udevice *dev) 166 { 167 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 168 int bank; 169 170 for (bank = 0; bank < priv->p_data->max_bank; bank++) { 171 if ((pin_num >= priv->p_data->bank_min[bank]) && 172 (pin_num <= priv->p_data->bank_max[bank])) { 173 *bank_num = bank; 174 *bank_pin_num = pin_num - 175 priv->p_data->bank_min[bank]; 176 return; 177 } 178 } 179 180 if (bank >= priv->p_data->max_bank) { 181 printf("Inavlid bank and pin num\n"); 182 *bank_num = 0; 183 *bank_pin_num = 0; 184 } 185 } 186 187 static int gpio_is_valid(unsigned gpio, struct udevice *dev) 188 { 189 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 190 191 return (gpio >= 0) && (gpio < priv->p_data->ngpio); 192 } 193 194 static int check_gpio(unsigned gpio, struct udevice *dev) 195 { 196 if (!gpio_is_valid(gpio, dev)) { 197 printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); 198 return -1; 199 } 200 return 0; 201 } 202 203 static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) 204 { 205 u32 data; 206 unsigned int bank_num, bank_pin_num; 207 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 208 209 if (check_gpio(gpio, dev) < 0) 210 return -1; 211 212 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 213 214 data = readl(priv->base + 215 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 216 217 return (data >> bank_pin_num) & 1; 218 } 219 220 static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) 221 { 222 unsigned int reg_offset, bank_num, bank_pin_num; 223 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 224 225 if (check_gpio(gpio, dev) < 0) 226 return -1; 227 228 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 229 230 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { 231 /* only 16 data bits in bit maskable reg */ 232 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; 233 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); 234 } else { 235 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); 236 } 237 238 /* 239 * get the 32 bit value to be written to the mask/data register where 240 * the upper 16 bits is the mask and lower 16 bits is the data 241 */ 242 value = !!value; 243 value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & 244 ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); 245 246 writel(value, priv->base + reg_offset); 247 248 return 0; 249 } 250 251 static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) 252 { 253 u32 reg; 254 unsigned int bank_num, bank_pin_num; 255 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 256 257 if (check_gpio(gpio, dev) < 0) 258 return -1; 259 260 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 261 262 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ 263 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) 264 return -1; 265 266 /* clear the bit in direction mode reg to set the pin as input */ 267 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 268 reg &= ~BIT(bank_pin_num); 269 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 270 271 return 0; 272 } 273 274 static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, 275 int value) 276 { 277 u32 reg; 278 unsigned int bank_num, bank_pin_num; 279 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 280 281 if (check_gpio(gpio, dev) < 0) 282 return -1; 283 284 zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); 285 286 /* set the GPIO pin as output */ 287 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 288 reg |= BIT(bank_pin_num); 289 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 290 291 /* configure the output enable reg for the pin */ 292 reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 293 reg |= BIT(bank_pin_num); 294 writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 295 296 /* set the state of the pin */ 297 gpio_set_value(gpio, value); 298 return 0; 299 } 300 301 static int zynq_gpio_get_function(struct udevice *dev, unsigned offset) 302 { 303 u32 reg; 304 unsigned int bank_num, bank_pin_num; 305 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 306 307 if (check_gpio(offset, dev) < 0) 308 return -1; 309 310 zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev); 311 312 /* set the GPIO pin as output */ 313 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 314 reg &= BIT(bank_pin_num); 315 if (reg) 316 return GPIOF_OUTPUT; 317 else 318 return GPIOF_INPUT; 319 } 320 321 static const struct dm_gpio_ops gpio_zynq_ops = { 322 .direction_input = zynq_gpio_direction_input, 323 .direction_output = zynq_gpio_direction_output, 324 .get_value = zynq_gpio_get_value, 325 .set_value = zynq_gpio_set_value, 326 .get_function = zynq_gpio_get_function, 327 }; 328 329 static const struct udevice_id zynq_gpio_ids[] = { 330 { .compatible = "xlnx,zynq-gpio-1.0", 331 .data = (ulong)&zynq_gpio_def}, 332 { .compatible = "xlnx,zynqmp-gpio-1.0", 333 .data = (ulong)&zynqmp_gpio_def}, 334 { } 335 }; 336 337 static void zynq_gpio_getplat_data(struct udevice *dev) 338 { 339 const struct udevice_id *of_match = zynq_gpio_ids; 340 int ret; 341 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 342 343 while (of_match->compatible) { 344 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 345 of_match->compatible); 346 if (ret >= 0) { 347 priv->p_data = 348 (struct zynq_platform_data *)of_match->data; 349 break; 350 } else { 351 of_match++; 352 continue; 353 } 354 } 355 356 if (!priv->p_data) 357 printf("No Platform data found\n"); 358 } 359 360 static int zynq_gpio_probe(struct udevice *dev) 361 { 362 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 363 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 364 365 zynq_gpio_getplat_data(dev); 366 367 if (priv->p_data) 368 uc_priv->gpio_count = priv->p_data->ngpio; 369 370 return 0; 371 } 372 373 static int zynq_gpio_ofdata_to_platdata(struct udevice *dev) 374 { 375 struct zynq_gpio_privdata *priv = dev_get_priv(dev); 376 377 priv->base = devfdt_get_addr(dev); 378 379 return 0; 380 } 381 382 U_BOOT_DRIVER(gpio_zynq) = { 383 .name = "gpio_zynq", 384 .id = UCLASS_GPIO, 385 .ops = &gpio_zynq_ops, 386 .of_match = zynq_gpio_ids, 387 .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata, 388 .probe = zynq_gpio_probe, 389 .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata), 390 }; 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