1 /* 2 * NVIDIA Tegra20 GPIO handling. 3 * (C) Copyright 2010-2012 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. 11 * Tom Warren (twarren@nvidia.com) 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <malloc.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <asm/io.h> 20 #include <asm/bitops.h> 21 #include <asm/arch/tegra.h> 22 #include <asm/gpio.h> 23 #include <dm/device-internal.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 enum { 28 TEGRA_CMD_INFO, 29 TEGRA_CMD_PORT, 30 TEGRA_CMD_OUTPUT, 31 TEGRA_CMD_INPUT, 32 }; 33 34 struct tegra_gpio_platdata { 35 struct gpio_ctlr_bank *bank; 36 const char *port_name; /* Name of port, e.g. "B" */ 37 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 38 }; 39 40 /* Information about each port at run-time */ 41 struct tegra_port_info { 42 char label[TEGRA_GPIOS_PER_PORT][GPIO_NAME_SIZE]; 43 struct gpio_ctlr_bank *bank; 44 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 45 }; 46 47 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ 48 static int get_config(unsigned gpio) 49 { 50 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 51 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 52 u32 u; 53 int type; 54 55 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 56 type = (u >> GPIO_BIT(gpio)) & 1; 57 58 debug("get_config: port = %d, bit = %d is %s\n", 59 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 60 61 return type; 62 } 63 64 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ 65 static void set_config(unsigned gpio, int type) 66 { 67 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 68 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 69 u32 u; 70 71 debug("set_config: port = %d, bit = %d, %s\n", 72 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 73 74 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 75 if (type) /* GPIO */ 76 u |= 1 << GPIO_BIT(gpio); 77 else 78 u &= ~(1 << GPIO_BIT(gpio)); 79 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); 80 } 81 82 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ 83 static int get_direction(unsigned gpio) 84 { 85 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 86 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 87 u32 u; 88 int dir; 89 90 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 91 dir = (u >> GPIO_BIT(gpio)) & 1; 92 93 debug("get_direction: port = %d, bit = %d, %s\n", 94 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); 95 96 return dir; 97 } 98 99 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ 100 static void set_direction(unsigned gpio, int output) 101 { 102 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 103 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 104 u32 u; 105 106 debug("set_direction: port = %d, bit = %d, %s\n", 107 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); 108 109 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 110 if (output) 111 u |= 1 << GPIO_BIT(gpio); 112 else 113 u &= ~(1 << GPIO_BIT(gpio)); 114 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); 115 } 116 117 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ 118 static void set_level(unsigned gpio, int high) 119 { 120 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 121 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 122 u32 u; 123 124 debug("set_level: port = %d, bit %d == %d\n", 125 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); 126 127 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); 128 if (high) 129 u |= 1 << GPIO_BIT(gpio); 130 else 131 u &= ~(1 << GPIO_BIT(gpio)); 132 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); 133 } 134 135 static int check_reserved(struct udevice *dev, unsigned offset, 136 const char *func) 137 { 138 struct tegra_port_info *state = dev_get_priv(dev); 139 struct gpio_dev_priv *uc_priv = dev->uclass_priv; 140 141 if (!*state->label[offset]) { 142 printf("tegra_gpio: %s: error: gpio %s%d not reserved\n", 143 func, uc_priv->bank_name, offset); 144 return -EBUSY; 145 } 146 147 return 0; 148 } 149 150 /* set GPIO pin 'gpio' as an output, with polarity 'value' */ 151 int tegra_spl_gpio_direction_output(int gpio, int value) 152 { 153 /* Configure as a GPIO */ 154 set_config(gpio, 1); 155 156 /* Configure GPIO output value. */ 157 set_level(gpio, value); 158 159 /* Configure GPIO direction as output. */ 160 set_direction(gpio, 1); 161 162 return 0; 163 } 164 165 /* 166 * Generic_GPIO primitives. 167 */ 168 169 static int tegra_gpio_request(struct udevice *dev, unsigned offset, 170 const char *label) 171 { 172 struct tegra_port_info *state = dev_get_priv(dev); 173 174 if (!label) 175 return -EINVAL; 176 177 if (*state->label[offset]) 178 return -EBUSY; 179 180 strncpy(state->label[offset], label, GPIO_NAME_SIZE); 181 state->label[offset][GPIO_NAME_SIZE - 1] = '\0'; 182 183 /* Configure as a GPIO */ 184 set_config(state->base_gpio + offset, 1); 185 186 return 0; 187 } 188 189 static int tegra_gpio_free(struct udevice *dev, unsigned offset) 190 { 191 struct tegra_port_info *state = dev_get_priv(dev); 192 int ret; 193 194 ret = check_reserved(dev, offset, __func__); 195 if (ret) 196 return ret; 197 state->label[offset][0] = '\0'; 198 199 return 0; 200 } 201 202 /* read GPIO OUT value of pin 'gpio' */ 203 static int tegra_gpio_get_output_value(unsigned gpio) 204 { 205 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 206 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 207 int val; 208 209 debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n", 210 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); 211 212 val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); 213 214 return (val >> GPIO_BIT(gpio)) & 1; 215 } 216 217 218 /* set GPIO pin 'gpio' as an input */ 219 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) 220 { 221 struct tegra_port_info *state = dev_get_priv(dev); 222 int ret; 223 224 ret = check_reserved(dev, offset, __func__); 225 if (ret) 226 return ret; 227 228 /* Configure GPIO direction as input. */ 229 set_direction(state->base_gpio + offset, 0); 230 231 return 0; 232 } 233 234 /* set GPIO pin 'gpio' as an output, with polarity 'value' */ 235 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, 236 int value) 237 { 238 struct tegra_port_info *state = dev_get_priv(dev); 239 int gpio = state->base_gpio + offset; 240 int ret; 241 242 ret = check_reserved(dev, offset, __func__); 243 if (ret) 244 return ret; 245 246 /* Configure GPIO output value. */ 247 set_level(gpio, value); 248 249 /* Configure GPIO direction as output. */ 250 set_direction(gpio, 1); 251 252 return 0; 253 } 254 255 /* read GPIO IN value of pin 'gpio' */ 256 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) 257 { 258 struct tegra_port_info *state = dev_get_priv(dev); 259 int gpio = state->base_gpio + offset; 260 int ret; 261 int val; 262 263 ret = check_reserved(dev, offset, __func__); 264 if (ret) 265 return ret; 266 267 debug("%s: pin = %d (port %d:bit %d)\n", __func__, 268 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); 269 270 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); 271 272 return (val >> GPIO_BIT(gpio)) & 1; 273 } 274 275 /* write GPIO OUT value to pin 'gpio' */ 276 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value) 277 { 278 struct tegra_port_info *state = dev_get_priv(dev); 279 int gpio = state->base_gpio + offset; 280 int ret; 281 282 ret = check_reserved(dev, offset, __func__); 283 if (ret) 284 return ret; 285 286 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", 287 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); 288 289 /* Configure GPIO output value. */ 290 set_level(gpio, value); 291 292 return 0; 293 } 294 295 void gpio_config_table(const struct tegra_gpio_config *config, int len) 296 { 297 int i; 298 299 for (i = 0; i < len; i++) { 300 switch (config[i].init) { 301 case TEGRA_GPIO_INIT_IN: 302 gpio_direction_input(config[i].gpio); 303 break; 304 case TEGRA_GPIO_INIT_OUT0: 305 gpio_direction_output(config[i].gpio, 0); 306 break; 307 case TEGRA_GPIO_INIT_OUT1: 308 gpio_direction_output(config[i].gpio, 1); 309 break; 310 } 311 set_config(config[i].gpio, 1); 312 } 313 } 314 315 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset) 316 { 317 struct tegra_port_info *state = dev_get_priv(dev); 318 int gpio = state->base_gpio + offset; 319 320 if (!*state->label[offset]) 321 return GPIOF_UNUSED; 322 if (!get_config(gpio)) 323 return GPIOF_FUNC; 324 else if (get_direction(gpio)) 325 return GPIOF_OUTPUT; 326 else 327 return GPIOF_INPUT; 328 } 329 330 static int tegra_gpio_get_state(struct udevice *dev, unsigned int offset, 331 char *buf, int bufsize) 332 { 333 struct gpio_dev_priv *uc_priv = dev->uclass_priv; 334 struct tegra_port_info *state = dev_get_priv(dev); 335 int gpio = state->base_gpio + offset; 336 const char *label; 337 int is_output; 338 int is_gpio; 339 int size; 340 341 label = state->label[offset]; 342 is_gpio = get_config(gpio); /* GPIO, not SFPIO */ 343 size = snprintf(buf, bufsize, "%s%d: ", 344 uc_priv->bank_name ? uc_priv->bank_name : "", offset); 345 buf += size; 346 bufsize -= size; 347 if (is_gpio) { 348 is_output = get_direction(gpio); 349 350 snprintf(buf, bufsize, "%s: %d [%c]%s%s", 351 is_output ? "out" : " in", 352 is_output ? 353 tegra_gpio_get_output_value(gpio) : 354 tegra_gpio_get_value(dev, offset), 355 *label ? 'x' : ' ', 356 *label ? " " : "", 357 label); 358 } else { 359 snprintf(buf, bufsize, "sfpio"); 360 } 361 362 return 0; 363 } 364 365 static const struct dm_gpio_ops gpio_tegra_ops = { 366 .request = tegra_gpio_request, 367 .free = tegra_gpio_free, 368 .direction_input = tegra_gpio_direction_input, 369 .direction_output = tegra_gpio_direction_output, 370 .get_value = tegra_gpio_get_value, 371 .set_value = tegra_gpio_set_value, 372 .get_function = tegra_gpio_get_function, 373 .get_state = tegra_gpio_get_state, 374 }; 375 376 /** 377 * Returns the name of a GPIO port 378 * 379 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ... 380 * 381 * @base_port: Base port number (0, 1..n-1) 382 * @return allocated string containing the name 383 */ 384 static char *gpio_port_name(int base_port) 385 { 386 char *name, *s; 387 388 name = malloc(3); 389 if (name) { 390 s = name; 391 *s++ = 'A' + (base_port % 26); 392 if (base_port >= 26) 393 *s++ = *name; 394 *s = '\0'; 395 } 396 397 return name; 398 } 399 400 static const struct udevice_id tegra_gpio_ids[] = { 401 { .compatible = "nvidia,tegra30-gpio" }, 402 { .compatible = "nvidia,tegra20-gpio" }, 403 { } 404 }; 405 406 static int gpio_tegra_probe(struct udevice *dev) 407 { 408 struct gpio_dev_priv *uc_priv = dev->uclass_priv; 409 struct tegra_port_info *priv = dev->priv; 410 struct tegra_gpio_platdata *plat = dev->platdata; 411 412 /* Only child devices have ports */ 413 if (!plat) 414 return 0; 415 416 priv->bank = plat->bank; 417 priv->base_gpio = plat->base_gpio; 418 419 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; 420 uc_priv->bank_name = plat->port_name; 421 422 return 0; 423 } 424 425 /** 426 * We have a top-level GPIO device with no actual GPIOs. It has a child 427 * device for each Tegra port. 428 */ 429 static int gpio_tegra_bind(struct udevice *parent) 430 { 431 struct tegra_gpio_platdata *plat = parent->platdata; 432 struct gpio_ctlr *ctlr; 433 int bank_count; 434 int bank; 435 int ret; 436 int len; 437 438 /* If this is a child device, there is nothing to do here */ 439 if (plat) 440 return 0; 441 442 /* 443 * This driver does not make use of interrupts, other than to figure 444 * out the number of GPIO banks 445 */ 446 if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len)) 447 return -EINVAL; 448 bank_count = len / 3 / sizeof(u32); 449 ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, 450 parent->of_offset, "reg"); 451 for (bank = 0; bank < bank_count; bank++) { 452 int port; 453 454 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { 455 struct tegra_gpio_platdata *plat; 456 struct udevice *dev; 457 int base_port; 458 459 plat = calloc(1, sizeof(*plat)); 460 if (!plat) 461 return -ENOMEM; 462 plat->bank = &ctlr->gpio_bank[bank]; 463 base_port = bank * TEGRA_PORTS_PER_BANK + port; 464 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; 465 plat->port_name = gpio_port_name(base_port); 466 467 ret = device_bind(parent, parent->driver, 468 plat->port_name, plat, -1, &dev); 469 if (ret) 470 return ret; 471 dev->of_offset = parent->of_offset; 472 } 473 } 474 475 return 0; 476 } 477 478 U_BOOT_DRIVER(gpio_tegra) = { 479 .name = "gpio_tegra", 480 .id = UCLASS_GPIO, 481 .of_match = tegra_gpio_ids, 482 .bind = gpio_tegra_bind, 483 .probe = gpio_tegra_probe, 484 .priv_auto_alloc_size = sizeof(struct tegra_port_info), 485 .ops = &gpio_tegra_ops, 486 }; 487