1 /* 2 * NVIDIA Tegra20 GPIO handling. 3 * (C) Copyright 2010-2012 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. 11 * Tom Warren (twarren@nvidia.com) 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <malloc.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <asm/io.h> 20 #include <asm/bitops.h> 21 #include <asm/arch/tegra.h> 22 #include <asm/gpio.h> 23 #include <dm/device-internal.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 enum { 28 TEGRA_CMD_INFO, 29 TEGRA_CMD_PORT, 30 TEGRA_CMD_OUTPUT, 31 TEGRA_CMD_INPUT, 32 }; 33 34 struct tegra_gpio_platdata { 35 struct gpio_ctlr_bank *bank; 36 const char *port_name; /* Name of port, e.g. "B" */ 37 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 38 }; 39 40 /* Information about each port at run-time */ 41 struct tegra_port_info { 42 struct gpio_ctlr_bank *bank; 43 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 44 }; 45 46 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ 47 static int get_config(unsigned gpio) 48 { 49 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 50 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 51 u32 u; 52 int type; 53 54 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 55 type = (u >> GPIO_BIT(gpio)) & 1; 56 57 debug("get_config: port = %d, bit = %d is %s\n", 58 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 59 60 return type; 61 } 62 63 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ 64 static void set_config(unsigned gpio, int type) 65 { 66 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 67 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 68 u32 u; 69 70 debug("set_config: port = %d, bit = %d, %s\n", 71 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 72 73 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 74 if (type) /* GPIO */ 75 u |= 1 << GPIO_BIT(gpio); 76 else 77 u &= ~(1 << GPIO_BIT(gpio)); 78 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); 79 } 80 81 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ 82 static int get_direction(unsigned gpio) 83 { 84 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 85 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 86 u32 u; 87 int dir; 88 89 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 90 dir = (u >> GPIO_BIT(gpio)) & 1; 91 92 debug("get_direction: port = %d, bit = %d, %s\n", 93 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); 94 95 return dir; 96 } 97 98 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ 99 static void set_direction(unsigned gpio, int output) 100 { 101 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 102 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 103 u32 u; 104 105 debug("set_direction: port = %d, bit = %d, %s\n", 106 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); 107 108 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 109 if (output) 110 u |= 1 << GPIO_BIT(gpio); 111 else 112 u &= ~(1 << GPIO_BIT(gpio)); 113 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); 114 } 115 116 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ 117 static void set_level(unsigned gpio, int high) 118 { 119 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 120 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 121 u32 u; 122 123 debug("set_level: port = %d, bit %d == %d\n", 124 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); 125 126 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); 127 if (high) 128 u |= 1 << GPIO_BIT(gpio); 129 else 130 u &= ~(1 << GPIO_BIT(gpio)); 131 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); 132 } 133 134 /* set GPIO pin 'gpio' as an output, with polarity 'value' */ 135 int tegra_spl_gpio_direction_output(int gpio, int value) 136 { 137 /* Configure as a GPIO */ 138 set_config(gpio, 1); 139 140 /* Configure GPIO output value. */ 141 set_level(gpio, value); 142 143 /* Configure GPIO direction as output. */ 144 set_direction(gpio, 1); 145 146 return 0; 147 } 148 149 /* 150 * Generic_GPIO primitives. 151 */ 152 153 static int tegra_gpio_request(struct udevice *dev, unsigned offset, 154 const char *label) 155 { 156 struct tegra_port_info *state = dev_get_priv(dev); 157 158 /* Configure as a GPIO */ 159 set_config(state->base_gpio + offset, 1); 160 161 return 0; 162 } 163 164 /* set GPIO pin 'gpio' as an input */ 165 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) 166 { 167 struct tegra_port_info *state = dev_get_priv(dev); 168 169 /* Configure GPIO direction as input. */ 170 set_direction(state->base_gpio + offset, 0); 171 172 return 0; 173 } 174 175 /* set GPIO pin 'gpio' as an output, with polarity 'value' */ 176 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, 177 int value) 178 { 179 struct tegra_port_info *state = dev_get_priv(dev); 180 int gpio = state->base_gpio + offset; 181 182 /* Configure GPIO output value. */ 183 set_level(gpio, value); 184 185 /* Configure GPIO direction as output. */ 186 set_direction(gpio, 1); 187 188 return 0; 189 } 190 191 /* read GPIO IN value of pin 'gpio' */ 192 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) 193 { 194 struct tegra_port_info *state = dev_get_priv(dev); 195 int gpio = state->base_gpio + offset; 196 int val; 197 198 debug("%s: pin = %d (port %d:bit %d)\n", __func__, 199 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); 200 201 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); 202 203 return (val >> GPIO_BIT(gpio)) & 1; 204 } 205 206 /* write GPIO OUT value to pin 'gpio' */ 207 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value) 208 { 209 struct tegra_port_info *state = dev_get_priv(dev); 210 int gpio = state->base_gpio + offset; 211 212 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", 213 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); 214 215 /* Configure GPIO output value. */ 216 set_level(gpio, value); 217 218 return 0; 219 } 220 221 void gpio_config_table(const struct tegra_gpio_config *config, int len) 222 { 223 int i; 224 225 for (i = 0; i < len; i++) { 226 switch (config[i].init) { 227 case TEGRA_GPIO_INIT_IN: 228 gpio_direction_input(config[i].gpio); 229 break; 230 case TEGRA_GPIO_INIT_OUT0: 231 gpio_direction_output(config[i].gpio, 0); 232 break; 233 case TEGRA_GPIO_INIT_OUT1: 234 gpio_direction_output(config[i].gpio, 1); 235 break; 236 } 237 set_config(config[i].gpio, 1); 238 } 239 } 240 241 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset) 242 { 243 struct tegra_port_info *state = dev_get_priv(dev); 244 int gpio = state->base_gpio + offset; 245 246 if (!get_config(gpio)) 247 return GPIOF_FUNC; 248 else if (get_direction(gpio)) 249 return GPIOF_OUTPUT; 250 else 251 return GPIOF_INPUT; 252 } 253 254 static const struct dm_gpio_ops gpio_tegra_ops = { 255 .request = tegra_gpio_request, 256 .direction_input = tegra_gpio_direction_input, 257 .direction_output = tegra_gpio_direction_output, 258 .get_value = tegra_gpio_get_value, 259 .set_value = tegra_gpio_set_value, 260 .get_function = tegra_gpio_get_function, 261 }; 262 263 /** 264 * Returns the name of a GPIO port 265 * 266 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ... 267 * 268 * @base_port: Base port number (0, 1..n-1) 269 * @return allocated string containing the name 270 */ 271 static char *gpio_port_name(int base_port) 272 { 273 char *name, *s; 274 275 name = malloc(3); 276 if (name) { 277 s = name; 278 *s++ = 'A' + (base_port % 26); 279 if (base_port >= 26) 280 *s++ = *name; 281 *s = '\0'; 282 } 283 284 return name; 285 } 286 287 static const struct udevice_id tegra_gpio_ids[] = { 288 { .compatible = "nvidia,tegra30-gpio" }, 289 { .compatible = "nvidia,tegra20-gpio" }, 290 { } 291 }; 292 293 static int gpio_tegra_probe(struct udevice *dev) 294 { 295 struct gpio_dev_priv *uc_priv = dev->uclass_priv; 296 struct tegra_port_info *priv = dev->priv; 297 struct tegra_gpio_platdata *plat = dev->platdata; 298 299 /* Only child devices have ports */ 300 if (!plat) 301 return 0; 302 303 priv->bank = plat->bank; 304 priv->base_gpio = plat->base_gpio; 305 306 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; 307 uc_priv->bank_name = plat->port_name; 308 309 return 0; 310 } 311 312 /** 313 * We have a top-level GPIO device with no actual GPIOs. It has a child 314 * device for each Tegra port. 315 */ 316 static int gpio_tegra_bind(struct udevice *parent) 317 { 318 struct tegra_gpio_platdata *plat = parent->platdata; 319 struct gpio_ctlr *ctlr; 320 int bank_count; 321 int bank; 322 int ret; 323 int len; 324 325 /* If this is a child device, there is nothing to do here */ 326 if (plat) 327 return 0; 328 329 /* 330 * This driver does not make use of interrupts, other than to figure 331 * out the number of GPIO banks 332 */ 333 if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len)) 334 return -EINVAL; 335 bank_count = len / 3 / sizeof(u32); 336 ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, 337 parent->of_offset, "reg"); 338 for (bank = 0; bank < bank_count; bank++) { 339 int port; 340 341 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { 342 struct tegra_gpio_platdata *plat; 343 struct udevice *dev; 344 int base_port; 345 346 plat = calloc(1, sizeof(*plat)); 347 if (!plat) 348 return -ENOMEM; 349 plat->bank = &ctlr->gpio_bank[bank]; 350 base_port = bank * TEGRA_PORTS_PER_BANK + port; 351 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; 352 plat->port_name = gpio_port_name(base_port); 353 354 ret = device_bind(parent, parent->driver, 355 plat->port_name, plat, -1, &dev); 356 if (ret) 357 return ret; 358 dev->of_offset = parent->of_offset; 359 } 360 } 361 362 return 0; 363 } 364 365 U_BOOT_DRIVER(gpio_tegra) = { 366 .name = "gpio_tegra", 367 .id = UCLASS_GPIO, 368 .of_match = tegra_gpio_ids, 369 .bind = gpio_tegra_bind, 370 .probe = gpio_tegra_probe, 371 .priv_auto_alloc_size = sizeof(struct tegra_port_info), 372 .ops = &gpio_tegra_ops, 373 }; 374