1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <asm/arch/gpio.h> 12 #include <asm/arch/stm32.h> 13 #include <asm/gpio.h> 14 #include <asm/io.h> 15 #include <linux/errno.h> 16 #include <linux/io.h> 17 18 #define MODE_BITS(gpio_pin) (gpio_pin * 2) 19 #define MODE_BITS_MASK 3 20 #define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16)) 21 22 /* 23 * convert gpio offset to gpio index taking into account gpio holes 24 * into gpio bank 25 */ 26 int stm32_offset_to_index(struct udevice *dev, unsigned int offset) 27 { 28 struct stm32_gpio_priv *priv = dev_get_priv(dev); 29 int idx = 0; 30 int i; 31 32 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) { 33 if (priv->gpio_range & BIT(i)) { 34 if (idx == offset) 35 return idx; 36 idx++; 37 } 38 } 39 /* shouldn't happen */ 40 return -EINVAL; 41 } 42 43 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) 44 { 45 struct stm32_gpio_priv *priv = dev_get_priv(dev); 46 struct stm32_gpio_regs *regs = priv->regs; 47 int bits_index; 48 int mask; 49 int idx; 50 51 idx = stm32_offset_to_index(dev, offset); 52 if (idx < 0) 53 return idx; 54 55 bits_index = MODE_BITS(idx); 56 mask = MODE_BITS_MASK << bits_index; 57 58 clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index); 59 60 return 0; 61 } 62 63 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset, 64 int value) 65 { 66 struct stm32_gpio_priv *priv = dev_get_priv(dev); 67 struct stm32_gpio_regs *regs = priv->regs; 68 int bits_index; 69 int mask; 70 int idx; 71 72 idx = stm32_offset_to_index(dev, offset); 73 if (idx < 0) 74 return idx; 75 76 bits_index = MODE_BITS(idx); 77 mask = MODE_BITS_MASK << bits_index; 78 79 clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index); 80 81 writel(BSRR_BIT(idx, value), ®s->bsrr); 82 83 return 0; 84 } 85 86 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset) 87 { 88 struct stm32_gpio_priv *priv = dev_get_priv(dev); 89 struct stm32_gpio_regs *regs = priv->regs; 90 int idx; 91 92 idx = stm32_offset_to_index(dev, offset); 93 if (idx < 0) 94 return idx; 95 96 return readl(®s->idr) & BIT(idx) ? 1 : 0; 97 } 98 99 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value) 100 { 101 struct stm32_gpio_priv *priv = dev_get_priv(dev); 102 struct stm32_gpio_regs *regs = priv->regs; 103 int idx; 104 105 idx = stm32_offset_to_index(dev, offset); 106 if (idx < 0) 107 return idx; 108 109 writel(BSRR_BIT(idx, value), ®s->bsrr); 110 111 return 0; 112 } 113 114 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset) 115 { 116 struct stm32_gpio_priv *priv = dev_get_priv(dev); 117 struct stm32_gpio_regs *regs = priv->regs; 118 int bits_index; 119 int mask; 120 int idx; 121 u32 mode; 122 123 idx = stm32_offset_to_index(dev, offset); 124 if (idx < 0) 125 return idx; 126 127 bits_index = MODE_BITS(idx); 128 mask = MODE_BITS_MASK << bits_index; 129 130 mode = (readl(®s->moder) & mask) >> bits_index; 131 if (mode == STM32_GPIO_MODE_OUT) 132 return GPIOF_OUTPUT; 133 if (mode == STM32_GPIO_MODE_IN) 134 return GPIOF_INPUT; 135 if (mode == STM32_GPIO_MODE_AN) 136 return GPIOF_UNUSED; 137 138 return GPIOF_FUNC; 139 } 140 141 static const struct dm_gpio_ops gpio_stm32_ops = { 142 .direction_input = stm32_gpio_direction_input, 143 .direction_output = stm32_gpio_direction_output, 144 .get_value = stm32_gpio_get_value, 145 .set_value = stm32_gpio_set_value, 146 .get_function = stm32_gpio_get_function, 147 }; 148 149 static int gpio_stm32_probe(struct udevice *dev) 150 { 151 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 152 struct stm32_gpio_priv *priv = dev_get_priv(dev); 153 struct ofnode_phandle_args args; 154 struct clk clk; 155 fdt_addr_t addr; 156 const char *name; 157 int ret; 158 int i; 159 160 addr = dev_read_addr(dev); 161 if (addr == FDT_ADDR_T_NONE) 162 return -EINVAL; 163 164 priv->regs = (struct stm32_gpio_regs *)addr; 165 name = dev_read_string(dev, "st,bank-name"); 166 if (!name) 167 return -EINVAL; 168 uc_priv->bank_name = name; 169 170 i = 0; 171 ret = dev_read_phandle_with_args(dev, "gpio-ranges", 172 NULL, 3, i, &args); 173 174 while (ret != -ENOENT) { 175 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1, 176 args.args[0]); 177 178 uc_priv->gpio_count += args.args[2]; 179 180 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, 181 ++i, &args); 182 } 183 184 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n", 185 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count, 186 priv->gpio_range); 187 188 ret = clk_get_by_index(dev, 0, &clk); 189 if (ret < 0) 190 return ret; 191 192 ret = clk_enable(&clk); 193 194 if (ret) { 195 dev_err(dev, "failed to enable clock\n"); 196 return ret; 197 } 198 debug("clock enabled for device %s\n", dev->name); 199 200 return 0; 201 } 202 203 static const struct udevice_id stm32_gpio_ids[] = { 204 { .compatible = "st,stm32-gpio" }, 205 { } 206 }; 207 208 U_BOOT_DRIVER(gpio_stm32) = { 209 .name = "gpio_stm32", 210 .id = UCLASS_GPIO, 211 .of_match = stm32_gpio_ids, 212 .probe = gpio_stm32_probe, 213 .ops = &gpio_stm32_ops, 214 .flags = DM_UC_FLAG_SEQ_ALIAS, 215 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv), 216 }; 217