1 /* 2 * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference. 3 * 4 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 */ 9 10 /* 11 * Note: 12 * The driver's compatible table is borrowed from Linux Kernel, 13 * but now max supported gpio pins is 24 and only PCA953X_TYPE 14 * is supported. PCA957X_TYPE is not supported now. 15 * Also the Polarity Inversion feature is not supported now. 16 * 17 * TODO: 18 * 1. Support PCA957X_TYPE 19 * 2. Support 24 gpio pins 20 * 3. Support Polarity Inversion 21 */ 22 23 #include <common.h> 24 #include <errno.h> 25 #include <dm.h> 26 #include <fdtdec.h> 27 #include <i2c.h> 28 #include <malloc.h> 29 #include <asm/gpio.h> 30 #include <asm/io.h> 31 #include <dt-bindings/gpio/gpio.h> 32 33 #define PCA953X_INPUT 0 34 #define PCA953X_OUTPUT 1 35 #define PCA953X_INVERT 2 36 #define PCA953X_DIRECTION 3 37 38 #define PCA_GPIO_MASK 0x00FF 39 #define PCA_INT 0x0100 40 #define PCA953X_TYPE 0x1000 41 #define PCA957X_TYPE 0x2000 42 #define PCA_TYPE_MASK 0xF000 43 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 44 45 enum { 46 PCA953X_DIRECTION_IN, 47 PCA953X_DIRECTION_OUT, 48 }; 49 50 #define MAX_BANK 5 51 #define BANK_SZ 8 52 53 /* 54 * struct pca953x_info - Data for pca953x 55 * 56 * @dev: udevice structure for the device 57 * @addr: i2c slave address 58 * @invert: Polarity inversion or not 59 * @gpio_count: the number of gpio pins that the device supports 60 * @chip_type: indicate the chip type,PCA953X or PCA957X 61 * @bank_count: the number of banks that the device supports 62 * @reg_output: array to hold the value of output registers 63 * @reg_direction: array to hold the value of direction registers 64 */ 65 struct pca953x_info { 66 struct udevice *dev; 67 int addr; 68 int invert; 69 int gpio_count; 70 int chip_type; 71 int bank_count; 72 u8 reg_output[MAX_BANK]; 73 u8 reg_direction[MAX_BANK]; 74 }; 75 76 static int pca953x_write_single(struct udevice *dev, int reg, u8 val, 77 int offset) 78 { 79 struct pca953x_info *info = dev_get_platdata(dev); 80 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ); 81 int off = offset / BANK_SZ; 82 int ret = 0; 83 84 ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1); 85 if (ret) { 86 dev_err(dev, "%s error\n", __func__); 87 return ret; 88 } 89 90 return 0; 91 } 92 93 static int pca953x_read_single(struct udevice *dev, int reg, u8 *val, 94 int offset) 95 { 96 struct pca953x_info *info = dev_get_platdata(dev); 97 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ); 98 int off = offset / BANK_SZ; 99 int ret; 100 u8 byte; 101 102 ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1); 103 if (ret) { 104 dev_err(dev, "%s error\n", __func__); 105 return ret; 106 } 107 108 *val = byte; 109 110 return 0; 111 } 112 113 static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val) 114 { 115 struct pca953x_info *info = dev_get_platdata(dev); 116 int ret = 0; 117 118 if (info->gpio_count <= 8) { 119 ret = dm_i2c_read(dev, reg, val, 1); 120 } else if (info->gpio_count <= 16) { 121 ret = dm_i2c_read(dev, reg << 1, val, info->bank_count); 122 } else if (info->gpio_count == 40) { 123 /* Auto increment */ 124 ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, 125 info->bank_count); 126 } else { 127 dev_err(dev, "Unsupported now\n"); 128 return -EINVAL; 129 } 130 131 return ret; 132 } 133 134 static int pca953x_is_output(struct udevice *dev, int offset) 135 { 136 struct pca953x_info *info = dev_get_platdata(dev); 137 138 int bank = offset / BANK_SZ; 139 int off = offset % BANK_SZ; 140 141 /*0: output; 1: input */ 142 return !(info->reg_direction[bank] & (1 << off)); 143 } 144 145 static int pca953x_get_value(struct udevice *dev, uint offset) 146 { 147 int ret; 148 u8 val = 0; 149 150 int off = offset % BANK_SZ; 151 152 ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset); 153 if (ret) 154 return ret; 155 156 return (val >> off) & 0x1; 157 } 158 159 static int pca953x_set_value(struct udevice *dev, uint offset, int value) 160 { 161 struct pca953x_info *info = dev_get_platdata(dev); 162 int bank = offset / BANK_SZ; 163 int off = offset % BANK_SZ; 164 u8 val; 165 int ret; 166 167 if (value) 168 val = info->reg_output[bank] | (1 << off); 169 else 170 val = info->reg_output[bank] & ~(1 << off); 171 172 ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset); 173 if (ret) 174 return ret; 175 176 info->reg_output[bank] = val; 177 178 return 0; 179 } 180 181 static int pca953x_set_direction(struct udevice *dev, uint offset, int dir) 182 { 183 struct pca953x_info *info = dev_get_platdata(dev); 184 int bank = offset / BANK_SZ; 185 int off = offset % BANK_SZ; 186 u8 val; 187 int ret; 188 189 if (dir == PCA953X_DIRECTION_IN) 190 val = info->reg_direction[bank] | (1 << off); 191 else 192 val = info->reg_direction[bank] & ~(1 << off); 193 194 ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset); 195 if (ret) 196 return ret; 197 198 info->reg_direction[bank] = val; 199 200 return 0; 201 } 202 203 static int pca953x_direction_input(struct udevice *dev, uint offset) 204 { 205 return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN); 206 } 207 208 static int pca953x_direction_output(struct udevice *dev, uint offset, int value) 209 { 210 /* Configure output value. */ 211 pca953x_set_value(dev, offset, value); 212 213 /* Configure direction as output. */ 214 pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT); 215 216 return 0; 217 } 218 219 static int pca953x_get_function(struct udevice *dev, uint offset) 220 { 221 if (pca953x_is_output(dev, offset)) 222 return GPIOF_OUTPUT; 223 else 224 return GPIOF_INPUT; 225 } 226 227 static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc, 228 struct ofnode_phandle_args *args) 229 { 230 desc->offset = args->args[0]; 231 desc->flags = args->args[1] & (GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0); 232 233 return 0; 234 } 235 236 static const struct dm_gpio_ops pca953x_ops = { 237 .direction_input = pca953x_direction_input, 238 .direction_output = pca953x_direction_output, 239 .get_value = pca953x_get_value, 240 .set_value = pca953x_set_value, 241 .get_function = pca953x_get_function, 242 .xlate = pca953x_xlate, 243 }; 244 245 static int pca953x_probe(struct udevice *dev) 246 { 247 struct pca953x_info *info = dev_get_platdata(dev); 248 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 249 char name[32], *str; 250 int addr; 251 ulong driver_data; 252 int ret; 253 254 addr = dev_read_addr(dev); 255 if (addr == 0) 256 return -ENODEV; 257 258 info->addr = addr; 259 260 driver_data = dev_get_driver_data(dev); 261 262 info->gpio_count = driver_data & PCA_GPIO_MASK; 263 if (info->gpio_count > MAX_BANK * BANK_SZ) { 264 dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ); 265 return -EINVAL; 266 } 267 268 info->chip_type = PCA_CHIP_TYPE(driver_data); 269 if (info->chip_type != PCA953X_TYPE) { 270 dev_err(dev, "Only support PCA953X chip type now.\n"); 271 return -EINVAL; 272 } 273 274 info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ); 275 276 ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output); 277 if (ret) { 278 dev_err(dev, "Error reading output register\n"); 279 return ret; 280 } 281 282 ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction); 283 if (ret) { 284 dev_err(dev, "Error reading direction register\n"); 285 return ret; 286 } 287 288 snprintf(name, sizeof(name), "gpio@%x_", info->addr); 289 str = strdup(name); 290 if (!str) 291 return -ENOMEM; 292 uc_priv->bank_name = str; 293 uc_priv->gpio_count = info->gpio_count; 294 295 dev_dbg(dev, "%s is ready\n", str); 296 297 return 0; 298 } 299 300 #define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int) 301 #define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int) 302 303 static const struct udevice_id pca953x_ids[] = { 304 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 305 { .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), }, 306 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 307 { .compatible = "nxp,pca9536", .data = OF_953X(4, 0), }, 308 { .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), }, 309 { .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), }, 310 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 311 { .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), }, 312 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 313 { .compatible = "nxp,pca9556", .data = OF_953X(8, 0), }, 314 { .compatible = "nxp,pca9557", .data = OF_953X(8, 0), }, 315 { .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), }, 316 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 317 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 318 319 { .compatible = "maxim,max7310", .data = OF_953X(8, 0), }, 320 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 321 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 322 { .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), }, 323 324 { .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), }, 325 { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), }, 326 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 327 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 328 329 { .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), }, 330 331 { .compatible = "exar,xra1202", .data = OF_953X(8, 0), }, 332 { } 333 }; 334 335 U_BOOT_DRIVER(pca953x) = { 336 .name = "pca953x", 337 .id = UCLASS_GPIO, 338 .ops = &pca953x_ops, 339 .probe = pca953x_probe, 340 .platdata_auto_alloc_size = sizeof(struct pca953x_info), 341 .of_match = pca953x_ids, 342 }; 343