1 /* 2 * (C) Copyright 2010 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <mvmfp.h> 12 #include <asm/arch/mfp.h> 13 14 /* 15 * mfp_config 16 * 17 * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin 18 * configuration registers to configure each GPIO/Function pin on the 19 * SoC. 20 * 21 * This function reads the array of values for 22 * MFPR_X registers and programms them into respective 23 * Multi-Function Pin registers. 24 * It supports - Alternate Function Selection programming. 25 * 26 * Whereas, 27 * The Configureation value is constructed using MFP() 28 * array consists of 32bit values as defined in MFP(xx,xx..) macro 29 */ 30 void mfp_config(u32 *mfp_cfgs) 31 { 32 u32 *p_mfpr = NULL; 33 u32 cfg_val, val; 34 35 do { 36 cfg_val = *mfp_cfgs++; 37 /* exit if End of configuration table detected */ 38 if (cfg_val == MFP_EOC) 39 break; 40 41 p_mfpr = (u32 *)(MV_MFPR_BASE 42 + MFP_REG_GET_OFFSET(cfg_val)); 43 44 /* Write a mfg register as per configuration */ 45 val = 0; 46 if (cfg_val & MFP_AF_FLAG) 47 /* Abstract and program Afternate-Func Selection */ 48 val |= cfg_val & MFP_AF_MASK; 49 if (cfg_val & MFP_EDGE_FLAG) 50 /* Abstract and program Edge configuration */ 51 val |= cfg_val & MFP_LPM_EDGE_MASK; 52 if (cfg_val & MFP_DRIVE_FLAG) 53 /* Abstract and program Drive configuration */ 54 val |= cfg_val & MFP_DRIVE_MASK; 55 if (cfg_val & MFP_PULL_FLAG) 56 /* Abstract and program Pullup/down configuration */ 57 val |= cfg_val & MFP_PULL_MASK; 58 59 writel(val, p_mfpr); 60 } while (1); 61 /* 62 * perform a read-back of any MFPR register to make sure the 63 * previous writings are finished 64 */ 65 readl(p_mfpr); 66 } 67