1 /* 2 * (C) Copyright 2011 3 * eInfochips Ltd. <www.einfochips.com> 4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> 5 * 6 * (C) Copyright 2010 7 * Marvell Semiconductor <www.marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __MVGPIO_H__ 13 #define __MVGPIO_H__ 14 15 #include <common.h> 16 17 /* 18 * GPIO Register map for Marvell SOCs 19 */ 20 struct gpio_reg { 21 u32 gplr; /* Pin Level Register - 0x0000 */ 22 u32 pad0[2]; 23 u32 gpdr; /* Pin Direction Register - 0x000C */ 24 u32 pad1[2]; 25 u32 gpsr; /* Pin Output Set Register - 0x0018 */ 26 u32 pad2[2]; 27 u32 gpcr; /* Pin Output Clear Register - 0x0024 */ 28 u32 pad3[2]; 29 u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ 30 u32 pad4[2]; 31 u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ 32 u32 pad5[2]; 33 u32 gedr; /* Edge Detect Status Register - 0x0048 */ 34 u32 pad6[2]; 35 u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ 36 u32 pad7[2]; 37 u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ 38 u32 pad8[2]; 39 u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable 40 Register - 0x006C */ 41 u32 pad9[2]; 42 u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable 43 Register - 0x0078 */ 44 u32 pad10[2]; 45 u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable 46 Register - 0x0084 */ 47 u32 pad11[2]; 48 u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable 49 Register - 0x0090 */ 50 u32 pad12[2]; 51 u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ 52 }; 53 54 #endif /* __MVGPIO_H__ */ 55