1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 /* 7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 8 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 9 * consisting of a standard header and a device-specific set of registers. PCI 10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 11 * other things). Within the PCI configuration space, the GPIOBASE register 12 * tells us where in the device's I/O region we can find more registers to 13 * actually access the GPIOs. 14 * 15 * PCI bus/device/function 0:1f:0 => PCI config registers 16 * PCI config register "GPIOBASE" 17 * PCI I/O space + [GPIOBASE] => start of GPIO registers 18 * GPIO registers => gpio pin function, direction, value 19 * 20 * 21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 22 * ICH versions have more, but the decoding the matrix that describes them is 23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 24 * but they will ONLY work for certain unspecified chipsets because the offset 25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 26 * reserved or subject to arcane restrictions. 27 */ 28 29 #include <common.h> 30 #include <dm.h> 31 #include <errno.h> 32 #include <fdtdec.h> 33 #include <pci.h> 34 #include <asm/gpio.h> 35 #include <asm/io.h> 36 37 #define GPIO_PER_BANK 32 38 39 /* Where in config space is the register that points to the GPIO registers? */ 40 #define PCI_CFG_GPIOBASE 0x48 41 42 struct ich6_bank_priv { 43 /* These are I/O addresses */ 44 uint32_t use_sel; 45 uint32_t io_sel; 46 uint32_t lvl; 47 }; 48 49 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) 50 { 51 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 52 pci_dev_t pci_dev; /* handle for 0:1f:0 */ 53 u8 tmpbyte; 54 u16 tmpword; 55 u32 tmplong; 56 u32 gpiobase; 57 int offset; 58 59 /* Where should it be? */ 60 pci_dev = PCI_BDF(0, 0x1f, 0); 61 62 /* Is the device present? */ 63 pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword); 64 if (tmpword != PCI_VENDOR_ID_INTEL) { 65 debug("%s: wrong VendorID\n", __func__); 66 return -ENODEV; 67 } 68 69 pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword); 70 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); 71 /* 72 * We'd like to validate the Device ID too, but pretty much any 73 * value is either a) correct with slight differences, or b) 74 * correct but undocumented. We'll have to check a bunch of other 75 * things instead... 76 */ 77 78 /* I/O should already be enabled (it's a RO bit). */ 79 pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword); 80 if (!(tmpword & PCI_COMMAND_IO)) { 81 debug("%s: device IO not enabled\n", __func__); 82 return -ENODEV; 83 } 84 85 /* Header Type must be normal (bits 6-0 only; see spec.) */ 86 pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte); 87 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 88 debug("%s: invalid Header type\n", __func__); 89 return -ENODEV; 90 } 91 92 /* Base Class must be a bridge device */ 93 pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte); 94 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 95 debug("%s: invalid class\n", __func__); 96 return -ENODEV; 97 } 98 /* Sub Class must be ISA */ 99 pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte); 100 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 101 debug("%s: invalid subclass\n", __func__); 102 return -ENODEV; 103 } 104 105 /* Programming Interface must be 0x00 (no others exist) */ 106 pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte); 107 if (tmpbyte != 0x00) { 108 debug("%s: invalid interface type\n", __func__); 109 return -ENODEV; 110 } 111 112 /* 113 * GPIOBASE moved to its current offset with ICH6, but prior to 114 * that it was unused (or undocumented). Check that it looks 115 * okay: not all ones or zeros, and mapped to I/O space (bit 0). 116 */ 117 pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong); 118 if (tmplong == 0x00000000 || tmplong == 0xffffffff || 119 !(tmplong & 0x00000001)) { 120 debug("%s: unexpected GPIOBASE value\n", __func__); 121 return -ENODEV; 122 } 123 124 /* 125 * Okay, I guess we're looking at the right device. The actual 126 * GPIO registers are in the PCI device's I/O space, starting 127 * at the offset that we just read. Bit 0 indicates that it's 128 * an I/O address, not a memory address, so mask that off. 129 */ 130 gpiobase = tmplong & 0xfffffffe; 131 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); 132 if (offset == -1) { 133 debug("%s: Invalid register offset %d\n", __func__, offset); 134 return -EINVAL; 135 } 136 plat->base_addr = gpiobase + offset; 137 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, 138 "bank-name", NULL); 139 140 return 0; 141 } 142 143 int ich6_gpio_probe(struct udevice *dev) 144 { 145 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 146 struct gpio_dev_priv *uc_priv = dev->uclass_priv; 147 struct ich6_bank_priv *bank = dev_get_priv(dev); 148 149 uc_priv->gpio_count = GPIO_PER_BANK; 150 uc_priv->bank_name = plat->bank_name; 151 bank->use_sel = plat->base_addr; 152 bank->io_sel = plat->base_addr + 4; 153 bank->lvl = plat->base_addr + 8; 154 155 return 0; 156 } 157 158 int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label) 159 { 160 struct ich6_bank_priv *bank = dev_get_priv(dev); 161 u32 tmplong; 162 163 /* 164 * Make sure that the GPIO pin we want isn't already in use for some 165 * built-in hardware function. We have to check this for every 166 * requested pin. 167 */ 168 tmplong = inl(bank->use_sel); 169 if (!(tmplong & (1UL << offset))) { 170 debug("%s: gpio %d is reserved for internal use\n", __func__, 171 offset); 172 return -EPERM; 173 } 174 175 return 0; 176 } 177 178 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) 179 { 180 struct ich6_bank_priv *bank = dev_get_priv(dev); 181 u32 tmplong; 182 183 tmplong = inl(bank->io_sel); 184 tmplong |= (1UL << offset); 185 outl(bank->io_sel, tmplong); 186 return 0; 187 } 188 189 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, 190 int value) 191 { 192 struct ich6_bank_priv *bank = dev_get_priv(dev); 193 u32 tmplong; 194 195 tmplong = inl(bank->io_sel); 196 tmplong &= ~(1UL << offset); 197 outl(bank->io_sel, tmplong); 198 return 0; 199 } 200 201 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) 202 203 { 204 struct ich6_bank_priv *bank = dev_get_priv(dev); 205 u32 tmplong; 206 int r; 207 208 tmplong = inl(bank->lvl); 209 r = (tmplong & (1UL << offset)) ? 1 : 0; 210 return r; 211 } 212 213 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, 214 int value) 215 { 216 struct ich6_bank_priv *bank = dev_get_priv(dev); 217 u32 tmplong; 218 219 tmplong = inl(bank->lvl); 220 if (value) 221 tmplong |= (1UL << offset); 222 else 223 tmplong &= ~(1UL << offset); 224 outl(bank->lvl, tmplong); 225 return 0; 226 } 227 228 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) 229 { 230 struct ich6_bank_priv *bank = dev_get_priv(dev); 231 u32 mask = 1UL << offset; 232 233 if (!(inl(bank->use_sel) & mask)) 234 return GPIOF_FUNC; 235 if (inl(bank->io_sel) & mask) 236 return GPIOF_INPUT; 237 else 238 return GPIOF_OUTPUT; 239 } 240 241 static const struct dm_gpio_ops gpio_ich6_ops = { 242 .request = ich6_gpio_request, 243 .direction_input = ich6_gpio_direction_input, 244 .direction_output = ich6_gpio_direction_output, 245 .get_value = ich6_gpio_get_value, 246 .set_value = ich6_gpio_set_value, 247 .get_function = ich6_gpio_get_function, 248 }; 249 250 static const struct udevice_id intel_ich6_gpio_ids[] = { 251 { .compatible = "intel,ich6-gpio" }, 252 { } 253 }; 254 255 U_BOOT_DRIVER(gpio_ich6) = { 256 .name = "gpio_ich6", 257 .id = UCLASS_GPIO, 258 .of_match = intel_ich6_gpio_ids, 259 .ops = &gpio_ich6_ops, 260 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, 261 .probe = ich6_gpio_probe, 262 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), 263 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), 264 }; 265