1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 /* 7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 8 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 9 * consisting of a standard header and a device-specific set of registers. PCI 10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 11 * other things). Within the PCI configuration space, the GPIOBASE register 12 * tells us where in the device's I/O region we can find more registers to 13 * actually access the GPIOs. 14 * 15 * PCI bus/device/function 0:1f:0 => PCI config registers 16 * PCI config register "GPIOBASE" 17 * PCI I/O space + [GPIOBASE] => start of GPIO registers 18 * GPIO registers => gpio pin function, direction, value 19 * 20 * 21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 22 * ICH versions have more, but the decoding the matrix that describes them is 23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 24 * but they will ONLY work for certain unspecified chipsets because the offset 25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 26 * reserved or subject to arcane restrictions. 27 */ 28 29 #include <common.h> 30 #include <dm.h> 31 #include <errno.h> 32 #include <fdtdec.h> 33 #include <pci.h> 34 #include <asm/gpio.h> 35 #include <asm/io.h> 36 #include <asm/pci.h> 37 38 #define GPIO_PER_BANK 32 39 40 struct ich6_bank_priv { 41 /* These are I/O addresses */ 42 uint16_t use_sel; 43 uint16_t io_sel; 44 uint16_t lvl; 45 }; 46 47 /* TODO: Move this to device tree, or platform data */ 48 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) 49 { 50 gd->arch.gpio_map = map; 51 } 52 53 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) 54 { 55 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 56 pci_dev_t pci_dev; /* handle for 0:1f:0 */ 57 u8 tmpbyte; 58 u16 tmpword; 59 u32 tmplong; 60 u16 gpiobase; 61 int offset; 62 63 /* Where should it be? */ 64 pci_dev = PCI_BDF(0, 0x1f, 0); 65 66 /* Is the device present? */ 67 tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID); 68 if (tmpword != PCI_VENDOR_ID_INTEL) { 69 debug("%s: wrong VendorID\n", __func__); 70 return -ENODEV; 71 } 72 73 tmpword = x86_pci_read_config16(pci_dev, PCI_DEVICE_ID); 74 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); 75 /* 76 * We'd like to validate the Device ID too, but pretty much any 77 * value is either a) correct with slight differences, or b) 78 * correct but undocumented. We'll have to check a bunch of other 79 * things instead... 80 */ 81 82 /* I/O should already be enabled (it's a RO bit). */ 83 tmpword = x86_pci_read_config16(pci_dev, PCI_COMMAND); 84 if (!(tmpword & PCI_COMMAND_IO)) { 85 debug("%s: device IO not enabled\n", __func__); 86 return -ENODEV; 87 } 88 89 /* Header Type must be normal (bits 6-0 only; see spec.) */ 90 tmpbyte = x86_pci_read_config8(pci_dev, PCI_HEADER_TYPE); 91 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 92 debug("%s: invalid Header type\n", __func__); 93 return -ENODEV; 94 } 95 96 /* Base Class must be a bridge device */ 97 tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_CODE); 98 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 99 debug("%s: invalid class\n", __func__); 100 return -ENODEV; 101 } 102 /* Sub Class must be ISA */ 103 tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); 104 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 105 debug("%s: invalid subclass\n", __func__); 106 return -ENODEV; 107 } 108 109 /* Programming Interface must be 0x00 (no others exist) */ 110 tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_PROG); 111 if (tmpbyte != 0x00) { 112 debug("%s: invalid interface type\n", __func__); 113 return -ENODEV; 114 } 115 116 /* 117 * GPIOBASE moved to its current offset with ICH6, but prior to 118 * that it was unused (or undocumented). Check that it looks 119 * okay: not all ones or zeros. 120 * 121 * Note we don't need check bit0 here, because the Tunnel Creek 122 * GPIO base address register bit0 is reserved (read returns 0), 123 * while on the Ivybridge the bit0 is used to indicate it is an 124 * I/O space. 125 */ 126 tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); 127 if (tmplong == 0x00000000 || tmplong == 0xffffffff) { 128 debug("%s: unexpected GPIOBASE value\n", __func__); 129 return -ENODEV; 130 } 131 132 /* 133 * Okay, I guess we're looking at the right device. The actual 134 * GPIO registers are in the PCI device's I/O space, starting 135 * at the offset that we just read. Bit 0 indicates that it's 136 * an I/O address, not a memory address, so mask that off. 137 */ 138 gpiobase = tmplong & 0xfffe; 139 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); 140 if (offset == -1) { 141 debug("%s: Invalid register offset %d\n", __func__, offset); 142 return -EINVAL; 143 } 144 plat->base_addr = gpiobase + offset; 145 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, 146 "bank-name", NULL); 147 148 return 0; 149 } 150 151 static int ich6_gpio_probe(struct udevice *dev) 152 { 153 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 154 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 155 struct ich6_bank_priv *bank = dev_get_priv(dev); 156 157 if (gd->arch.gpio_map) { 158 setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); 159 gd->arch.gpio_map = NULL; 160 } 161 162 uc_priv->gpio_count = GPIO_PER_BANK; 163 uc_priv->bank_name = plat->bank_name; 164 bank->use_sel = plat->base_addr; 165 bank->io_sel = plat->base_addr + 4; 166 bank->lvl = plat->base_addr + 8; 167 168 return 0; 169 } 170 171 static int ich6_gpio_request(struct udevice *dev, unsigned offset, 172 const char *label) 173 { 174 struct ich6_bank_priv *bank = dev_get_priv(dev); 175 u32 tmplong; 176 177 /* 178 * Make sure that the GPIO pin we want isn't already in use for some 179 * built-in hardware function. We have to check this for every 180 * requested pin. 181 */ 182 tmplong = inl(bank->use_sel); 183 if (!(tmplong & (1UL << offset))) { 184 debug("%s: gpio %d is reserved for internal use\n", __func__, 185 offset); 186 return -EPERM; 187 } 188 189 return 0; 190 } 191 192 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) 193 { 194 struct ich6_bank_priv *bank = dev_get_priv(dev); 195 u32 tmplong; 196 197 tmplong = inl(bank->io_sel); 198 tmplong |= (1UL << offset); 199 outl(bank->io_sel, tmplong); 200 return 0; 201 } 202 203 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, 204 int value) 205 { 206 struct ich6_bank_priv *bank = dev_get_priv(dev); 207 u32 tmplong; 208 209 gpio_set_value(offset, value); 210 211 tmplong = inl(bank->io_sel); 212 tmplong &= ~(1UL << offset); 213 outl(bank->io_sel, tmplong); 214 return 0; 215 } 216 217 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) 218 219 { 220 struct ich6_bank_priv *bank = dev_get_priv(dev); 221 u32 tmplong; 222 int r; 223 224 tmplong = inl(bank->lvl); 225 r = (tmplong & (1UL << offset)) ? 1 : 0; 226 return r; 227 } 228 229 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, 230 int value) 231 { 232 struct ich6_bank_priv *bank = dev_get_priv(dev); 233 u32 tmplong; 234 235 tmplong = inl(bank->lvl); 236 if (value) 237 tmplong |= (1UL << offset); 238 else 239 tmplong &= ~(1UL << offset); 240 outl(bank->lvl, tmplong); 241 return 0; 242 } 243 244 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) 245 { 246 struct ich6_bank_priv *bank = dev_get_priv(dev); 247 u32 mask = 1UL << offset; 248 249 if (!(inl(bank->use_sel) & mask)) 250 return GPIOF_FUNC; 251 if (inl(bank->io_sel) & mask) 252 return GPIOF_INPUT; 253 else 254 return GPIOF_OUTPUT; 255 } 256 257 static const struct dm_gpio_ops gpio_ich6_ops = { 258 .request = ich6_gpio_request, 259 .direction_input = ich6_gpio_direction_input, 260 .direction_output = ich6_gpio_direction_output, 261 .get_value = ich6_gpio_get_value, 262 .set_value = ich6_gpio_set_value, 263 .get_function = ich6_gpio_get_function, 264 }; 265 266 static const struct udevice_id intel_ich6_gpio_ids[] = { 267 { .compatible = "intel,ich6-gpio" }, 268 { } 269 }; 270 271 U_BOOT_DRIVER(gpio_ich6) = { 272 .name = "gpio_ich6", 273 .id = UCLASS_GPIO, 274 .of_match = intel_ich6_gpio_ids, 275 .ops = &gpio_ich6_ops, 276 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, 277 .probe = ich6_gpio_probe, 278 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), 279 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), 280 }; 281