1 /*
2  * Copyright (c) 2012 The Chromium OS Authors.
3  * SPDX-License-Identifier:	GPL-2.0+
4  */
5 
6 /*
7  * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8  * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9  * consisting of a standard header and a device-specific set of registers. PCI
10  * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11  * other things). Within the PCI configuration space, the GPIOBASE register
12  * tells us where in the device's I/O region we can find more registers to
13  * actually access the GPIOs.
14  *
15  * PCI bus/device/function 0:1f:0  => PCI config registers
16  *   PCI config register "GPIOBASE"
17  *     PCI I/O space + [GPIOBASE]  => start of GPIO registers
18  *       GPIO registers => gpio pin function, direction, value
19  *
20  *
21  * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22  * ICH versions have more, but the decoding the matrix that describes them is
23  * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24  * but they will ONLY work for certain unspecified chipsets because the offset
25  * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26  * reserved or subject to arcane restrictions.
27  */
28 
29 #include <common.h>
30 #include <dm.h>
31 #include <errno.h>
32 #include <fdtdec.h>
33 #include <pci.h>
34 #include <asm/gpio.h>
35 #include <asm/io.h>
36 #include <asm/pci.h>
37 
38 DECLARE_GLOBAL_DATA_PTR;
39 
40 #define GPIO_PER_BANK	32
41 
42 struct ich6_bank_priv {
43 	/* These are I/O addresses */
44 	uint16_t use_sel;
45 	uint16_t io_sel;
46 	uint16_t lvl;
47 };
48 
49 #define GPIO_USESEL_OFFSET(x)	(x)
50 #define GPIO_IOSEL_OFFSET(x)	(x + 4)
51 #define GPIO_LVL_OFFSET(x)	(x + 8)
52 
53 #define IOPAD_MODE_MASK				0x7
54 #define IOPAD_PULL_ASSIGN_SHIFT		7
55 #define IOPAD_PULL_ASSIGN_MASK		(0x3 << IOPAD_PULL_ASSIGN_SHIFT)
56 #define IOPAD_PULL_STRENGTH_SHIFT	9
57 #define IOPAD_PULL_STRENGTH_MASK	(0x3 << IOPAD_PULL_STRENGTH_SHIFT)
58 
59 /* TODO: Move this to device tree, or platform data */
60 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
61 {
62 	gd->arch.gpio_map = map;
63 }
64 
65 static int gpio_ich6_get_base(unsigned long base)
66 {
67 	pci_dev_t pci_dev;			/* handle for 0:1f:0 */
68 	u8 tmpbyte;
69 	u16 tmpword;
70 	u32 tmplong;
71 
72 	/* Where should it be? */
73 	pci_dev = PCI_BDF(0, 0x1f, 0);
74 
75 	/* Is the device present? */
76 	tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID);
77 	if (tmpword != PCI_VENDOR_ID_INTEL) {
78 		debug("%s: wrong VendorID\n", __func__);
79 		return -ENODEV;
80 	}
81 
82 	tmpword = x86_pci_read_config16(pci_dev, PCI_DEVICE_ID);
83 	debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
84 	/*
85 	 * We'd like to validate the Device ID too, but pretty much any
86 	 * value is either a) correct with slight differences, or b)
87 	 * correct but undocumented. We'll have to check a bunch of other
88 	 * things instead...
89 	 */
90 
91 	/* I/O should already be enabled (it's a RO bit). */
92 	tmpword = x86_pci_read_config16(pci_dev, PCI_COMMAND);
93 	if (!(tmpword & PCI_COMMAND_IO)) {
94 		debug("%s: device IO not enabled\n", __func__);
95 		return -ENODEV;
96 	}
97 
98 	/* Header Type must be normal (bits 6-0 only; see spec.) */
99 	tmpbyte = x86_pci_read_config8(pci_dev, PCI_HEADER_TYPE);
100 	if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
101 		debug("%s: invalid Header type\n", __func__);
102 		return -ENODEV;
103 	}
104 
105 	/* Base Class must be a bridge device */
106 	tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_CODE);
107 	if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
108 		debug("%s: invalid class\n", __func__);
109 		return -ENODEV;
110 	}
111 	/* Sub Class must be ISA */
112 	tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
113 	if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
114 		debug("%s: invalid subclass\n", __func__);
115 		return -ENODEV;
116 	}
117 
118 	/* Programming Interface must be 0x00 (no others exist) */
119 	tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_PROG);
120 	if (tmpbyte != 0x00) {
121 		debug("%s: invalid interface type\n", __func__);
122 		return -ENODEV;
123 	}
124 
125 	/*
126 	 * GPIOBASE moved to its current offset with ICH6, but prior to
127 	 * that it was unused (or undocumented). Check that it looks
128 	 * okay: not all ones or zeros.
129 	 *
130 	 * Note we don't need check bit0 here, because the Tunnel Creek
131 	 * GPIO base address register bit0 is reserved (read returns 0),
132 	 * while on the Ivybridge the bit0 is used to indicate it is an
133 	 * I/O space.
134 	 */
135 	tmplong = x86_pci_read_config32(pci_dev, base);
136 	if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
137 		debug("%s: unexpected BASE value\n", __func__);
138 		return -ENODEV;
139 	}
140 
141 	/*
142 	 * Okay, I guess we're looking at the right device. The actual
143 	 * GPIO registers are in the PCI device's I/O space, starting
144 	 * at the offset that we just read. Bit 0 indicates that it's
145 	 * an I/O address, not a memory address, so mask that off.
146 	 */
147 	return tmplong & 0xfffc;
148 }
149 
150 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
151 {
152 	u32 val;
153 
154 	val = inl(base);
155 	if (value)
156 		val |= (1UL << offset);
157 	else
158 		val &= ~(1UL << offset);
159 	outl(val, base);
160 
161 	return 0;
162 }
163 
164 static int _ich6_gpio_set_function(uint16_t base, unsigned offset, int func)
165 {
166 	u32 val;
167 
168 	if (func) {
169 		val = inl(base);
170 		val |= (1UL << offset);
171 		outl(val, base);
172 	} else {
173 		val = inl(base);
174 		val &= ~(1UL << offset);
175 		outl(val, base);
176 	}
177 
178 	return 0;
179 }
180 
181 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
182 {
183 	u32 val;
184 
185 	if (!dir) {
186 		val = inl(base);
187 		val |= (1UL << offset);
188 		outl(val, base);
189 	} else {
190 		val = inl(base);
191 		val &= ~(1UL << offset);
192 		outl(val, base);
193 	}
194 
195 	return 0;
196 }
197 
198 static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
199 {
200 	u32 gpio_offset[2];
201 	int pad_offset;
202 	int val;
203 	int ret;
204 	const void *prop;
205 
206 	/*
207 	 * GPIO node is not mandatory, so we only do the
208 	 * pinmuxing if the node exist.
209 	 */
210 	ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
211 			     gpio_offset, 2);
212 	if (!ret) {
213 		/* Do we want to force the GPIO mode? */
214 		prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio",
215 				      NULL);
216 		if (prop)
217 			_ich6_gpio_set_function(GPIO_USESEL_OFFSET
218 						(gpiobase) +
219 						gpio_offset[0],
220 						gpio_offset[1], 1);
221 
222 		val =
223 		    fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
224 		if (val != -1)
225 			_ich6_gpio_set_direction(GPIO_IOSEL_OFFSET
226 						 (gpiobase) +
227 						 gpio_offset[0],
228 						 gpio_offset[1], val);
229 
230 		val =
231 		    fdtdec_get_int(gd->fdt_blob, pin_node, "output-value", -1);
232 		if (val != -1)
233 			_ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase)
234 					     + gpio_offset[0],
235 					     gpio_offset[1], val);
236 	}
237 
238 	/* if iobase is present, let's configure the pad */
239 	if (iobase != -1) {
240 		int iobase_addr;
241 
242 		/*
243 		 * The offset for the same pin for the IOBASE and GPIOBASE are
244 		 * different, so instead of maintaining a lookup table,
245 		 * the device tree should provide directly the correct
246 		 * value for both mapping.
247 		 */
248 		pad_offset =
249 		    fdtdec_get_int(gd->fdt_blob, pin_node, "pad-offset", -1);
250 		if (pad_offset == -1) {
251 			debug("%s: Invalid register io offset %d\n",
252 			      __func__, pad_offset);
253 			return -EINVAL;
254 		}
255 
256 		/* compute the absolute pad address */
257 		iobase_addr = iobase + pad_offset;
258 
259 		/*
260 		 * Do we need to set a specific function mode?
261 		 * If someone put also 'mode-gpio', this option will
262 		 * be just ignored by the controller
263 		 */
264 		val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
265 		if (val != -1)
266 			clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
267 
268 		/* Configure the pull-up/down if needed */
269 		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
270 		if (val != -1)
271 			clrsetbits_le32(iobase_addr,
272 					IOPAD_PULL_ASSIGN_MASK,
273 					val << IOPAD_PULL_ASSIGN_SHIFT);
274 
275 		val =
276 		    fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength", -1);
277 		if (val != -1)
278 			clrsetbits_le32(iobase_addr,
279 					IOPAD_PULL_STRENGTH_MASK,
280 					val << IOPAD_PULL_STRENGTH_SHIFT);
281 
282 		debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
283 		      readl(iobase_addr));
284 	}
285 
286 	return 0;
287 }
288 
289 int gpio_ich6_pinctrl_init(void)
290 {
291 	int pin_node;
292 	int node;
293 	int ret;
294 	int gpiobase;
295 	int iobase_offset;
296 	int iobase = -1;
297 
298 	/*
299 	 * Get the memory/io base address to configure every pins.
300 	 * IOBASE is used to configure the mode/pads
301 	 * GPIOBASE is used to configure the direction and default value
302 	 */
303 	gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE);
304 	if (gpiobase < 0) {
305 		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
306 		      gpiobase);
307 		return -EINVAL;
308 	}
309 
310 	/* This is not an error to not have a pinctrl node */
311 	node =
312 	    fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_X86_PINCTRL);
313 	if (node <= 0) {
314 		debug("%s: no pinctrl node\n", __func__);
315 		return 0;
316 	}
317 
318 	/*
319 	 * Get the IOBASE, this is not mandatory as this is not
320 	 * supported by all the CPU
321 	 */
322 	iobase_offset = fdtdec_get_int(gd->fdt_blob, node, "io-base", -1);
323 	if (iobase_offset == -1) {
324 		debug("%s: io-base offset not present\n", __func__);
325 	} else {
326 		iobase = gpio_ich6_get_base(iobase_offset);
327 		if (iobase < 0) {
328 			debug("%s: invalid IOBASE address (%08x)\n", __func__,
329 			      iobase);
330 			return -EINVAL;
331 		}
332 	}
333 
334 	for (pin_node = fdt_first_subnode(gd->fdt_blob, node);
335 	     pin_node > 0;
336 	     pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
337 		/* Configure the pin */
338 		ret = _gpio_ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
339 		if (ret != 0) {
340 			debug("%s: invalid configuration for the pin %d\n",
341 			      __func__, pin_node);
342 			return ret;
343 		}
344 	}
345 
346 	return 0;
347 }
348 
349 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
350 {
351 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
352 	u16 gpiobase;
353 	int offset;
354 
355 	gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE);
356 	offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
357 	if (offset == -1) {
358 		debug("%s: Invalid register offset %d\n", __func__, offset);
359 		return -EINVAL;
360 	}
361 	plat->base_addr = gpiobase + offset;
362 	plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
363 				      "bank-name", NULL);
364 
365 	return 0;
366 }
367 
368 static int ich6_gpio_probe(struct udevice *dev)
369 {
370 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
371 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
372 	struct ich6_bank_priv *bank = dev_get_priv(dev);
373 
374 	if (gd->arch.gpio_map) {
375 		setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
376 		gd->arch.gpio_map = NULL;
377 	}
378 
379 	uc_priv->gpio_count = GPIO_PER_BANK;
380 	uc_priv->bank_name = plat->bank_name;
381 	bank->use_sel = plat->base_addr;
382 	bank->io_sel = plat->base_addr + 4;
383 	bank->lvl = plat->base_addr + 8;
384 
385 	return 0;
386 }
387 
388 static int ich6_gpio_request(struct udevice *dev, unsigned offset,
389 			     const char *label)
390 {
391 	struct ich6_bank_priv *bank = dev_get_priv(dev);
392 	u32 tmplong;
393 
394 	/*
395 	 * Make sure that the GPIO pin we want isn't already in use for some
396 	 * built-in hardware function. We have to check this for every
397 	 * requested pin.
398 	 */
399 	tmplong = inl(bank->use_sel);
400 	if (!(tmplong & (1UL << offset))) {
401 		debug("%s: gpio %d is reserved for internal use\n", __func__,
402 		      offset);
403 		return -EPERM;
404 	}
405 
406 	return 0;
407 }
408 
409 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
410 {
411 	struct ich6_bank_priv *bank = dev_get_priv(dev);
412 
413 	return _ich6_gpio_set_direction(inl(bank->io_sel), offset, 0);
414 }
415 
416 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
417 				       int value)
418 {
419 	int ret;
420 	struct ich6_bank_priv *bank = dev_get_priv(dev);
421 
422 	ret = _ich6_gpio_set_direction(inl(bank->io_sel), offset, 1);
423 	if (ret)
424 		return ret;
425 
426 	return _ich6_gpio_set_value(bank->lvl, offset, value);
427 }
428 
429 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
430 {
431 	struct ich6_bank_priv *bank = dev_get_priv(dev);
432 	u32 tmplong;
433 	int r;
434 
435 	tmplong = inl(bank->lvl);
436 	r = (tmplong & (1UL << offset)) ? 1 : 0;
437 	return r;
438 }
439 
440 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
441 			       int value)
442 {
443 	struct ich6_bank_priv *bank = dev_get_priv(dev);
444 	return _ich6_gpio_set_value(bank->lvl, offset, value);
445 }
446 
447 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
448 {
449 	struct ich6_bank_priv *bank = dev_get_priv(dev);
450 	u32 mask = 1UL << offset;
451 
452 	if (!(inl(bank->use_sel) & mask))
453 		return GPIOF_FUNC;
454 	if (inl(bank->io_sel) & mask)
455 		return GPIOF_INPUT;
456 	else
457 		return GPIOF_OUTPUT;
458 }
459 
460 static const struct dm_gpio_ops gpio_ich6_ops = {
461 	.request		= ich6_gpio_request,
462 	.direction_input	= ich6_gpio_direction_input,
463 	.direction_output	= ich6_gpio_direction_output,
464 	.get_value		= ich6_gpio_get_value,
465 	.set_value		= ich6_gpio_set_value,
466 	.get_function		= ich6_gpio_get_function,
467 };
468 
469 static const struct udevice_id intel_ich6_gpio_ids[] = {
470 	{ .compatible = "intel,ich6-gpio" },
471 	{ }
472 };
473 
474 U_BOOT_DRIVER(gpio_ich6) = {
475 	.name	= "gpio_ich6",
476 	.id	= UCLASS_GPIO,
477 	.of_match = intel_ich6_gpio_ids,
478 	.ops	= &gpio_ich6_ops,
479 	.ofdata_to_platdata	= gpio_ich6_ofdata_to_platdata,
480 	.probe	= ich6_gpio_probe,
481 	.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
482 	.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
483 };
484