1 /*
2  * Copyright (c) 2012 The Chromium OS Authors.
3  * SPDX-License-Identifier:	GPL-2.0+
4  */
5 
6 /*
7  * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8  * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9  * consisting of a standard header and a device-specific set of registers. PCI
10  * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11  * other things). Within the PCI configuration space, the GPIOBASE register
12  * tells us where in the device's I/O region we can find more registers to
13  * actually access the GPIOs.
14  *
15  * PCI bus/device/function 0:1f:0  => PCI config registers
16  *   PCI config register "GPIOBASE"
17  *     PCI I/O space + [GPIOBASE]  => start of GPIO registers
18  *       GPIO registers => gpio pin function, direction, value
19  *
20  *
21  * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22  * ICH versions have more, but the decoding the matrix that describes them is
23  * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24  * but they will ONLY work for certain unspecified chipsets because the offset
25  * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26  * reserved or subject to arcane restrictions.
27  */
28 
29 #include <common.h>
30 #include <dm.h>
31 #include <errno.h>
32 #include <fdtdec.h>
33 #include <pch.h>
34 #include <pci.h>
35 #include <asm/gpio.h>
36 #include <asm/io.h>
37 #include <asm/pci.h>
38 
39 DECLARE_GLOBAL_DATA_PTR;
40 
41 #define GPIO_PER_BANK	32
42 
43 struct ich6_bank_priv {
44 	/* These are I/O addresses */
45 	uint16_t use_sel;
46 	uint16_t io_sel;
47 	uint16_t lvl;
48 };
49 
50 #define GPIO_USESEL_OFFSET(x)	(x)
51 #define GPIO_IOSEL_OFFSET(x)	(x + 4)
52 #define GPIO_LVL_OFFSET(x)	(x + 8)
53 
54 #define IOPAD_MODE_MASK				0x7
55 #define IOPAD_PULL_ASSIGN_SHIFT		7
56 #define IOPAD_PULL_ASSIGN_MASK		(0x3 << IOPAD_PULL_ASSIGN_SHIFT)
57 #define IOPAD_PULL_STRENGTH_SHIFT	9
58 #define IOPAD_PULL_STRENGTH_MASK	(0x3 << IOPAD_PULL_STRENGTH_SHIFT)
59 
60 /* TODO: Move this to device tree, or platform data */
61 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
62 {
63 	gd->arch.gpio_map = map;
64 }
65 
66 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
67 {
68 	u32 val;
69 
70 	val = inl(base);
71 	if (value)
72 		val |= (1UL << offset);
73 	else
74 		val &= ~(1UL << offset);
75 	outl(val, base);
76 
77 	return 0;
78 }
79 
80 static int _ich6_gpio_set_function(uint16_t base, unsigned offset, int func)
81 {
82 	u32 val;
83 
84 	if (func) {
85 		val = inl(base);
86 		val |= (1UL << offset);
87 		outl(val, base);
88 	} else {
89 		val = inl(base);
90 		val &= ~(1UL << offset);
91 		outl(val, base);
92 	}
93 
94 	return 0;
95 }
96 
97 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
98 {
99 	u32 val;
100 
101 	if (!dir) {
102 		val = inl(base);
103 		val |= (1UL << offset);
104 		outl(val, base);
105 	} else {
106 		val = inl(base);
107 		val &= ~(1UL << offset);
108 		outl(val, base);
109 	}
110 
111 	return 0;
112 }
113 
114 static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
115 {
116 	u32 gpio_offset[2];
117 	int pad_offset;
118 	int val;
119 	int ret;
120 	const void *prop;
121 
122 	/*
123 	 * GPIO node is not mandatory, so we only do the
124 	 * pinmuxing if the node exist.
125 	 */
126 	ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
127 			     gpio_offset, 2);
128 	if (!ret) {
129 		/* Do we want to force the GPIO mode? */
130 		prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio",
131 				      NULL);
132 		if (prop)
133 			_ich6_gpio_set_function(GPIO_USESEL_OFFSET
134 						(gpiobase) +
135 						gpio_offset[0],
136 						gpio_offset[1], 1);
137 
138 		val =
139 		    fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
140 		if (val != -1)
141 			_ich6_gpio_set_direction(GPIO_IOSEL_OFFSET
142 						 (gpiobase) +
143 						 gpio_offset[0],
144 						 gpio_offset[1], val);
145 
146 		val =
147 		    fdtdec_get_int(gd->fdt_blob, pin_node, "output-value", -1);
148 		if (val != -1)
149 			_ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase)
150 					     + gpio_offset[0],
151 					     gpio_offset[1], val);
152 	}
153 
154 	/* if iobase is present, let's configure the pad */
155 	if (iobase != -1) {
156 		int iobase_addr;
157 
158 		/*
159 		 * The offset for the same pin for the IOBASE and GPIOBASE are
160 		 * different, so instead of maintaining a lookup table,
161 		 * the device tree should provide directly the correct
162 		 * value for both mapping.
163 		 */
164 		pad_offset =
165 		    fdtdec_get_int(gd->fdt_blob, pin_node, "pad-offset", -1);
166 		if (pad_offset == -1) {
167 			debug("%s: Invalid register io offset %d\n",
168 			      __func__, pad_offset);
169 			return -EINVAL;
170 		}
171 
172 		/* compute the absolute pad address */
173 		iobase_addr = iobase + pad_offset;
174 
175 		/*
176 		 * Do we need to set a specific function mode?
177 		 * If someone put also 'mode-gpio', this option will
178 		 * be just ignored by the controller
179 		 */
180 		val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
181 		if (val != -1)
182 			clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
183 
184 		/* Configure the pull-up/down if needed */
185 		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
186 		if (val != -1)
187 			clrsetbits_le32(iobase_addr,
188 					IOPAD_PULL_ASSIGN_MASK,
189 					val << IOPAD_PULL_ASSIGN_SHIFT);
190 
191 		val =
192 		    fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength", -1);
193 		if (val != -1)
194 			clrsetbits_le32(iobase_addr,
195 					IOPAD_PULL_STRENGTH_MASK,
196 					val << IOPAD_PULL_STRENGTH_SHIFT);
197 
198 		debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
199 		      readl(iobase_addr));
200 	}
201 
202 	return 0;
203 }
204 
205 int gpio_ich6_pinctrl_init(void)
206 {
207 	struct udevice *pch;
208 	int pin_node;
209 	int node;
210 	int ret;
211 	u32 gpiobase;
212 	u32 iobase = -1;
213 
214 	ret = uclass_first_device(UCLASS_PCH, &pch);
215 	if (ret)
216 		return ret;
217 	if (!pch)
218 		return -ENODEV;
219 
220 	/*
221 	 * Get the memory/io base address to configure every pins.
222 	 * IOBASE is used to configure the mode/pads
223 	 * GPIOBASE is used to configure the direction and default value
224 	 */
225 	ret = pch_get_gpio_base(pch, &gpiobase);
226 	if (ret) {
227 		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
228 		      gpiobase);
229 		return -EINVAL;
230 	}
231 
232 	/* This is not an error to not have a pinctrl node */
233 	node =
234 	    fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_X86_PINCTRL);
235 	if (node <= 0) {
236 		debug("%s: no pinctrl node\n", __func__);
237 		return 0;
238 	}
239 
240 	/*
241 	 * Get the IOBASE, this is not mandatory as this is not
242 	 * supported by all the CPU
243 	 */
244 	ret = pch_get_io_base(pch, &iobase);
245 	if (ret && ret != -ENOSYS) {
246 		debug("%s: invalid IOBASE address (%08x)\n", __func__,
247 		      iobase);
248 		return -EINVAL;
249 	}
250 
251 	for (pin_node = fdt_first_subnode(gd->fdt_blob, node);
252 	     pin_node > 0;
253 	     pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
254 		/* Configure the pin */
255 		ret = _gpio_ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
256 		if (ret != 0) {
257 			debug("%s: invalid configuration for the pin %d\n",
258 			      __func__, pin_node);
259 			return ret;
260 		}
261 	}
262 
263 	return 0;
264 }
265 
266 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
267 {
268 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
269 	u32 gpiobase;
270 	int offset;
271 	int ret;
272 
273 	ret = pch_get_gpio_base(dev->parent, &gpiobase);
274 	if (ret)
275 		return ret;
276 
277 	offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
278 	if (offset == -1) {
279 		debug("%s: Invalid register offset %d\n", __func__, offset);
280 		return -EINVAL;
281 	}
282 	plat->offset = offset;
283 	plat->base_addr = gpiobase + offset;
284 	plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
285 				      "bank-name", NULL);
286 
287 	return 0;
288 }
289 
290 static int ich6_gpio_probe(struct udevice *dev)
291 {
292 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
293 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
294 	struct ich6_bank_priv *bank = dev_get_priv(dev);
295 
296 	if (gd->arch.gpio_map) {
297 		setup_pch_gpios(plat->base_addr - plat->offset,
298 				gd->arch.gpio_map);
299 		gd->arch.gpio_map = NULL;
300 	}
301 
302 	uc_priv->gpio_count = GPIO_PER_BANK;
303 	uc_priv->bank_name = plat->bank_name;
304 	bank->use_sel = plat->base_addr;
305 	bank->io_sel = plat->base_addr + 4;
306 	bank->lvl = plat->base_addr + 8;
307 
308 	return 0;
309 }
310 
311 static int ich6_gpio_request(struct udevice *dev, unsigned offset,
312 			     const char *label)
313 {
314 	struct ich6_bank_priv *bank = dev_get_priv(dev);
315 	u32 tmplong;
316 
317 	/*
318 	 * Make sure that the GPIO pin we want isn't already in use for some
319 	 * built-in hardware function. We have to check this for every
320 	 * requested pin.
321 	 */
322 	tmplong = inl(bank->use_sel);
323 	if (!(tmplong & (1UL << offset))) {
324 		debug("%s: gpio %d is reserved for internal use\n", __func__,
325 		      offset);
326 		return -EPERM;
327 	}
328 
329 	return 0;
330 }
331 
332 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
333 {
334 	struct ich6_bank_priv *bank = dev_get_priv(dev);
335 
336 	return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
337 }
338 
339 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
340 				       int value)
341 {
342 	int ret;
343 	struct ich6_bank_priv *bank = dev_get_priv(dev);
344 
345 	ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
346 	if (ret)
347 		return ret;
348 
349 	return _ich6_gpio_set_value(bank->lvl, offset, value);
350 }
351 
352 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
353 {
354 	struct ich6_bank_priv *bank = dev_get_priv(dev);
355 	u32 tmplong;
356 	int r;
357 
358 	tmplong = inl(bank->lvl);
359 	r = (tmplong & (1UL << offset)) ? 1 : 0;
360 	return r;
361 }
362 
363 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
364 			       int value)
365 {
366 	struct ich6_bank_priv *bank = dev_get_priv(dev);
367 	return _ich6_gpio_set_value(bank->lvl, offset, value);
368 }
369 
370 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
371 {
372 	struct ich6_bank_priv *bank = dev_get_priv(dev);
373 	u32 mask = 1UL << offset;
374 
375 	if (!(inl(bank->use_sel) & mask))
376 		return GPIOF_FUNC;
377 	if (inl(bank->io_sel) & mask)
378 		return GPIOF_INPUT;
379 	else
380 		return GPIOF_OUTPUT;
381 }
382 
383 static const struct dm_gpio_ops gpio_ich6_ops = {
384 	.request		= ich6_gpio_request,
385 	.direction_input	= ich6_gpio_direction_input,
386 	.direction_output	= ich6_gpio_direction_output,
387 	.get_value		= ich6_gpio_get_value,
388 	.set_value		= ich6_gpio_set_value,
389 	.get_function		= ich6_gpio_get_function,
390 };
391 
392 static const struct udevice_id intel_ich6_gpio_ids[] = {
393 	{ .compatible = "intel,ich6-gpio" },
394 	{ }
395 };
396 
397 U_BOOT_DRIVER(gpio_ich6) = {
398 	.name	= "gpio_ich6",
399 	.id	= UCLASS_GPIO,
400 	.of_match = intel_ich6_gpio_ids,
401 	.ops	= &gpio_ich6_ops,
402 	.ofdata_to_platdata	= gpio_ich6_ofdata_to_platdata,
403 	.probe	= ich6_gpio_probe,
404 	.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
405 	.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
406 };
407