1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 /* 7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 8 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 9 * consisting of a standard header and a device-specific set of registers. PCI 10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 11 * other things). Within the PCI configuration space, the GPIOBASE register 12 * tells us where in the device's I/O region we can find more registers to 13 * actually access the GPIOs. 14 * 15 * PCI bus/device/function 0:1f:0 => PCI config registers 16 * PCI config register "GPIOBASE" 17 * PCI I/O space + [GPIOBASE] => start of GPIO registers 18 * GPIO registers => gpio pin function, direction, value 19 * 20 * 21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 22 * ICH versions have more, but the decoding the matrix that describes them is 23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 24 * but they will ONLY work for certain unspecified chipsets because the offset 25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 26 * reserved or subject to arcane restrictions. 27 */ 28 29 #include <common.h> 30 #include <dm.h> 31 #include <errno.h> 32 #include <fdtdec.h> 33 #include <pci.h> 34 #include <asm/gpio.h> 35 #include <asm/io.h> 36 #include <asm/pci.h> 37 #ifdef CONFIG_X86_RESET_VECTOR 38 #include <asm/arch/pch.h> 39 #define SUPPORT_GPIO_SETUP 40 #endif 41 42 #define GPIO_PER_BANK 32 43 44 /* Where in config space is the register that points to the GPIO registers? */ 45 #define PCI_CFG_GPIOBASE 0x48 46 47 struct ich6_bank_priv { 48 /* These are I/O addresses */ 49 uint32_t use_sel; 50 uint32_t io_sel; 51 uint32_t lvl; 52 }; 53 54 #ifdef SUPPORT_GPIO_SETUP 55 static void setup_pch_gpios(const struct pch_gpio_map *gpio) 56 { 57 u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; 58 59 /* GPIO Set 1 */ 60 if (gpio->set1.level) 61 outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); 62 if (gpio->set1.mode) 63 outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); 64 if (gpio->set1.direction) 65 outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); 66 if (gpio->set1.reset) 67 outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); 68 if (gpio->set1.invert) 69 outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); 70 if (gpio->set1.blink) 71 outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); 72 73 /* GPIO Set 2 */ 74 if (gpio->set2.level) 75 outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); 76 if (gpio->set2.mode) 77 outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); 78 if (gpio->set2.direction) 79 outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); 80 if (gpio->set2.reset) 81 outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); 82 83 /* GPIO Set 3 */ 84 if (gpio->set3.level) 85 outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); 86 if (gpio->set3.mode) 87 outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); 88 if (gpio->set3.direction) 89 outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); 90 if (gpio->set3.reset) 91 outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); 92 } 93 94 /* TODO: Move this to device tree, or platform data */ 95 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) 96 { 97 gd->arch.gpio_map = map; 98 } 99 #endif /* SUPPORT_GPIO_SETUP */ 100 101 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) 102 { 103 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 104 pci_dev_t pci_dev; /* handle for 0:1f:0 */ 105 u8 tmpbyte; 106 u16 tmpword; 107 u32 tmplong; 108 u32 gpiobase; 109 int offset; 110 111 /* Where should it be? */ 112 pci_dev = PCI_BDF(0, 0x1f, 0); 113 114 /* Is the device present? */ 115 tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID); 116 if (tmpword != PCI_VENDOR_ID_INTEL) { 117 debug("%s: wrong VendorID\n", __func__); 118 return -ENODEV; 119 } 120 121 tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID); 122 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); 123 /* 124 * We'd like to validate the Device ID too, but pretty much any 125 * value is either a) correct with slight differences, or b) 126 * correct but undocumented. We'll have to check a bunch of other 127 * things instead... 128 */ 129 130 /* I/O should already be enabled (it's a RO bit). */ 131 tmpword = pci_read_config16(pci_dev, PCI_COMMAND); 132 if (!(tmpword & PCI_COMMAND_IO)) { 133 debug("%s: device IO not enabled\n", __func__); 134 return -ENODEV; 135 } 136 137 /* Header Type must be normal (bits 6-0 only; see spec.) */ 138 tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE); 139 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 140 debug("%s: invalid Header type\n", __func__); 141 return -ENODEV; 142 } 143 144 /* Base Class must be a bridge device */ 145 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE); 146 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 147 debug("%s: invalid class\n", __func__); 148 return -ENODEV; 149 } 150 /* Sub Class must be ISA */ 151 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); 152 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 153 debug("%s: invalid subclass\n", __func__); 154 return -ENODEV; 155 } 156 157 /* Programming Interface must be 0x00 (no others exist) */ 158 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG); 159 if (tmpbyte != 0x00) { 160 debug("%s: invalid interface type\n", __func__); 161 return -ENODEV; 162 } 163 164 /* 165 * GPIOBASE moved to its current offset with ICH6, but prior to 166 * that it was unused (or undocumented). Check that it looks 167 * okay: not all ones or zeros, and mapped to I/O space (bit 0). 168 */ 169 tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); 170 if (tmplong == 0x00000000 || tmplong == 0xffffffff || 171 !(tmplong & 0x00000001)) { 172 debug("%s: unexpected GPIOBASE value\n", __func__); 173 return -ENODEV; 174 } 175 176 /* 177 * Okay, I guess we're looking at the right device. The actual 178 * GPIO registers are in the PCI device's I/O space, starting 179 * at the offset that we just read. Bit 0 indicates that it's 180 * an I/O address, not a memory address, so mask that off. 181 */ 182 gpiobase = tmplong & 0xfffffffe; 183 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); 184 if (offset == -1) { 185 debug("%s: Invalid register offset %d\n", __func__, offset); 186 return -EINVAL; 187 } 188 plat->base_addr = gpiobase + offset; 189 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, 190 "bank-name", NULL); 191 192 return 0; 193 } 194 195 static int ich6_gpio_probe(struct udevice *dev) 196 { 197 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 198 struct gpio_dev_priv *uc_priv = dev->uclass_priv; 199 struct ich6_bank_priv *bank = dev_get_priv(dev); 200 201 #ifdef SUPPORT_GPIO_SETUP 202 if (gd->arch.gpio_map) { 203 setup_pch_gpios(gd->arch.gpio_map); 204 gd->arch.gpio_map = NULL; 205 } 206 #endif 207 uc_priv->gpio_count = GPIO_PER_BANK; 208 uc_priv->bank_name = plat->bank_name; 209 bank->use_sel = plat->base_addr; 210 bank->io_sel = plat->base_addr + 4; 211 bank->lvl = plat->base_addr + 8; 212 213 return 0; 214 } 215 216 static int ich6_gpio_request(struct udevice *dev, unsigned offset, 217 const char *label) 218 { 219 struct ich6_bank_priv *bank = dev_get_priv(dev); 220 u32 tmplong; 221 222 /* 223 * Make sure that the GPIO pin we want isn't already in use for some 224 * built-in hardware function. We have to check this for every 225 * requested pin. 226 */ 227 tmplong = inl(bank->use_sel); 228 if (!(tmplong & (1UL << offset))) { 229 debug("%s: gpio %d is reserved for internal use\n", __func__, 230 offset); 231 return -EPERM; 232 } 233 234 return 0; 235 } 236 237 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) 238 { 239 struct ich6_bank_priv *bank = dev_get_priv(dev); 240 u32 tmplong; 241 242 tmplong = inl(bank->io_sel); 243 tmplong |= (1UL << offset); 244 outl(bank->io_sel, tmplong); 245 return 0; 246 } 247 248 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, 249 int value) 250 { 251 struct ich6_bank_priv *bank = dev_get_priv(dev); 252 u32 tmplong; 253 254 tmplong = inl(bank->io_sel); 255 tmplong &= ~(1UL << offset); 256 outl(bank->io_sel, tmplong); 257 return 0; 258 } 259 260 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) 261 262 { 263 struct ich6_bank_priv *bank = dev_get_priv(dev); 264 u32 tmplong; 265 int r; 266 267 tmplong = inl(bank->lvl); 268 r = (tmplong & (1UL << offset)) ? 1 : 0; 269 return r; 270 } 271 272 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, 273 int value) 274 { 275 struct ich6_bank_priv *bank = dev_get_priv(dev); 276 u32 tmplong; 277 278 tmplong = inl(bank->lvl); 279 if (value) 280 tmplong |= (1UL << offset); 281 else 282 tmplong &= ~(1UL << offset); 283 outl(bank->lvl, tmplong); 284 return 0; 285 } 286 287 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) 288 { 289 struct ich6_bank_priv *bank = dev_get_priv(dev); 290 u32 mask = 1UL << offset; 291 292 if (!(inl(bank->use_sel) & mask)) 293 return GPIOF_FUNC; 294 if (inl(bank->io_sel) & mask) 295 return GPIOF_INPUT; 296 else 297 return GPIOF_OUTPUT; 298 } 299 300 static const struct dm_gpio_ops gpio_ich6_ops = { 301 .request = ich6_gpio_request, 302 .direction_input = ich6_gpio_direction_input, 303 .direction_output = ich6_gpio_direction_output, 304 .get_value = ich6_gpio_get_value, 305 .set_value = ich6_gpio_set_value, 306 .get_function = ich6_gpio_get_function, 307 }; 308 309 static const struct udevice_id intel_ich6_gpio_ids[] = { 310 { .compatible = "intel,ich6-gpio" }, 311 { } 312 }; 313 314 U_BOOT_DRIVER(gpio_ich6) = { 315 .name = "gpio_ich6", 316 .id = UCLASS_GPIO, 317 .of_match = intel_ich6_gpio_ids, 318 .ops = &gpio_ich6_ops, 319 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, 320 .probe = ich6_gpio_probe, 321 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), 322 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), 323 }; 324