1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 /* 7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 8 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 9 * consisting of a standard header and a device-specific set of registers. PCI 10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 11 * other things). Within the PCI configuration space, the GPIOBASE register 12 * tells us where in the device's I/O region we can find more registers to 13 * actually access the GPIOs. 14 * 15 * PCI bus/device/function 0:1f:0 => PCI config registers 16 * PCI config register "GPIOBASE" 17 * PCI I/O space + [GPIOBASE] => start of GPIO registers 18 * GPIO registers => gpio pin function, direction, value 19 * 20 * 21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 22 * ICH versions have more, but the decoding the matrix that describes them is 23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 24 * but they will ONLY work for certain unspecified chipsets because the offset 25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 26 * reserved or subject to arcane restrictions. 27 */ 28 29 #include <common.h> 30 #include <dm.h> 31 #include <errno.h> 32 #include <fdtdec.h> 33 #include <pci.h> 34 #include <asm/gpio.h> 35 #include <asm/io.h> 36 #include <asm/pci.h> 37 38 #define GPIO_PER_BANK 32 39 40 struct ich6_bank_priv { 41 /* These are I/O addresses */ 42 uint32_t use_sel; 43 uint32_t io_sel; 44 uint32_t lvl; 45 }; 46 47 /* TODO: Move this to device tree, or platform data */ 48 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) 49 { 50 gd->arch.gpio_map = map; 51 } 52 53 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) 54 { 55 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 56 pci_dev_t pci_dev; /* handle for 0:1f:0 */ 57 u8 tmpbyte; 58 u16 tmpword; 59 u32 tmplong; 60 u32 gpiobase; 61 int offset; 62 63 /* Where should it be? */ 64 pci_dev = PCI_BDF(0, 0x1f, 0); 65 66 /* Is the device present? */ 67 tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID); 68 if (tmpword != PCI_VENDOR_ID_INTEL) { 69 debug("%s: wrong VendorID\n", __func__); 70 return -ENODEV; 71 } 72 73 tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID); 74 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); 75 /* 76 * We'd like to validate the Device ID too, but pretty much any 77 * value is either a) correct with slight differences, or b) 78 * correct but undocumented. We'll have to check a bunch of other 79 * things instead... 80 */ 81 82 /* I/O should already be enabled (it's a RO bit). */ 83 tmpword = pci_read_config16(pci_dev, PCI_COMMAND); 84 if (!(tmpword & PCI_COMMAND_IO)) { 85 debug("%s: device IO not enabled\n", __func__); 86 return -ENODEV; 87 } 88 89 /* Header Type must be normal (bits 6-0 only; see spec.) */ 90 tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE); 91 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 92 debug("%s: invalid Header type\n", __func__); 93 return -ENODEV; 94 } 95 96 /* Base Class must be a bridge device */ 97 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE); 98 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 99 debug("%s: invalid class\n", __func__); 100 return -ENODEV; 101 } 102 /* Sub Class must be ISA */ 103 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); 104 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 105 debug("%s: invalid subclass\n", __func__); 106 return -ENODEV; 107 } 108 109 /* Programming Interface must be 0x00 (no others exist) */ 110 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG); 111 if (tmpbyte != 0x00) { 112 debug("%s: invalid interface type\n", __func__); 113 return -ENODEV; 114 } 115 116 /* 117 * GPIOBASE moved to its current offset with ICH6, but prior to 118 * that it was unused (or undocumented). Check that it looks 119 * okay: not all ones or zeros, and mapped to I/O space (bit 0). 120 */ 121 tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); 122 if (tmplong == 0x00000000 || tmplong == 0xffffffff || 123 !(tmplong & 0x00000001)) { 124 debug("%s: unexpected GPIOBASE value\n", __func__); 125 return -ENODEV; 126 } 127 128 /* 129 * Okay, I guess we're looking at the right device. The actual 130 * GPIO registers are in the PCI device's I/O space, starting 131 * at the offset that we just read. Bit 0 indicates that it's 132 * an I/O address, not a memory address, so mask that off. 133 */ 134 gpiobase = tmplong & 0xfffffffe; 135 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); 136 if (offset == -1) { 137 debug("%s: Invalid register offset %d\n", __func__, offset); 138 return -EINVAL; 139 } 140 plat->base_addr = gpiobase + offset; 141 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, 142 "bank-name", NULL); 143 144 return 0; 145 } 146 147 static int ich6_gpio_probe(struct udevice *dev) 148 { 149 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 150 struct gpio_dev_priv *uc_priv = dev->uclass_priv; 151 struct ich6_bank_priv *bank = dev_get_priv(dev); 152 153 if (gd->arch.gpio_map) { 154 setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); 155 gd->arch.gpio_map = NULL; 156 } 157 158 uc_priv->gpio_count = GPIO_PER_BANK; 159 uc_priv->bank_name = plat->bank_name; 160 bank->use_sel = plat->base_addr; 161 bank->io_sel = plat->base_addr + 4; 162 bank->lvl = plat->base_addr + 8; 163 164 return 0; 165 } 166 167 static int ich6_gpio_request(struct udevice *dev, unsigned offset, 168 const char *label) 169 { 170 struct ich6_bank_priv *bank = dev_get_priv(dev); 171 u32 tmplong; 172 173 /* 174 * Make sure that the GPIO pin we want isn't already in use for some 175 * built-in hardware function. We have to check this for every 176 * requested pin. 177 */ 178 tmplong = inl(bank->use_sel); 179 if (!(tmplong & (1UL << offset))) { 180 debug("%s: gpio %d is reserved for internal use\n", __func__, 181 offset); 182 return -EPERM; 183 } 184 185 return 0; 186 } 187 188 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) 189 { 190 struct ich6_bank_priv *bank = dev_get_priv(dev); 191 u32 tmplong; 192 193 tmplong = inl(bank->io_sel); 194 tmplong |= (1UL << offset); 195 outl(bank->io_sel, tmplong); 196 return 0; 197 } 198 199 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, 200 int value) 201 { 202 struct ich6_bank_priv *bank = dev_get_priv(dev); 203 u32 tmplong; 204 205 gpio_set_value(offset, value); 206 207 tmplong = inl(bank->io_sel); 208 tmplong &= ~(1UL << offset); 209 outl(bank->io_sel, tmplong); 210 return 0; 211 } 212 213 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) 214 215 { 216 struct ich6_bank_priv *bank = dev_get_priv(dev); 217 u32 tmplong; 218 int r; 219 220 tmplong = inl(bank->lvl); 221 r = (tmplong & (1UL << offset)) ? 1 : 0; 222 return r; 223 } 224 225 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, 226 int value) 227 { 228 struct ich6_bank_priv *bank = dev_get_priv(dev); 229 u32 tmplong; 230 231 tmplong = inl(bank->lvl); 232 if (value) 233 tmplong |= (1UL << offset); 234 else 235 tmplong &= ~(1UL << offset); 236 outl(bank->lvl, tmplong); 237 return 0; 238 } 239 240 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) 241 { 242 struct ich6_bank_priv *bank = dev_get_priv(dev); 243 u32 mask = 1UL << offset; 244 245 if (!(inl(bank->use_sel) & mask)) 246 return GPIOF_FUNC; 247 if (inl(bank->io_sel) & mask) 248 return GPIOF_INPUT; 249 else 250 return GPIOF_OUTPUT; 251 } 252 253 static const struct dm_gpio_ops gpio_ich6_ops = { 254 .request = ich6_gpio_request, 255 .direction_input = ich6_gpio_direction_input, 256 .direction_output = ich6_gpio_direction_output, 257 .get_value = ich6_gpio_get_value, 258 .set_value = ich6_gpio_set_value, 259 .get_function = ich6_gpio_get_function, 260 }; 261 262 static const struct udevice_id intel_ich6_gpio_ids[] = { 263 { .compatible = "intel,ich6-gpio" }, 264 { } 265 }; 266 267 U_BOOT_DRIVER(gpio_ich6) = { 268 .name = "gpio_ich6", 269 .id = UCLASS_GPIO, 270 .of_match = intel_ich6_gpio_ids, 271 .ops = &gpio_ich6_ops, 272 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, 273 .probe = ich6_gpio_probe, 274 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), 275 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), 276 }; 277