1 /*
2  * Copyright (c) 2012 The Chromium OS Authors.
3  * SPDX-License-Identifier:	GPL-2.0+
4  */
5 
6 /*
7  * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8  * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9  * consisting of a standard header and a device-specific set of registers. PCI
10  * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11  * other things). Within the PCI configuration space, the GPIOBASE register
12  * tells us where in the device's I/O region we can find more registers to
13  * actually access the GPIOs.
14  *
15  * PCI bus/device/function 0:1f:0  => PCI config registers
16  *   PCI config register "GPIOBASE"
17  *     PCI I/O space + [GPIOBASE]  => start of GPIO registers
18  *       GPIO registers => gpio pin function, direction, value
19  *
20  *
21  * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22  * ICH versions have more, but the decoding the matrix that describes them is
23  * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24  * but they will ONLY work for certain unspecified chipsets because the offset
25  * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26  * reserved or subject to arcane restrictions.
27  */
28 
29 #include <common.h>
30 #include <dm.h>
31 #include <errno.h>
32 #include <fdtdec.h>
33 #include <pch.h>
34 #include <pci.h>
35 #include <asm/cpu.h>
36 #include <asm/gpio.h>
37 #include <asm/io.h>
38 #include <asm/pci.h>
39 
40 DECLARE_GLOBAL_DATA_PTR;
41 
42 #define GPIO_PER_BANK	32
43 
44 struct ich6_bank_priv {
45 	/* These are I/O addresses */
46 	uint16_t use_sel;
47 	uint16_t io_sel;
48 	uint16_t lvl;
49 };
50 
51 #define GPIO_USESEL_OFFSET(x)	(x)
52 #define GPIO_IOSEL_OFFSET(x)	(x + 4)
53 #define GPIO_LVL_OFFSET(x)	(x + 8)
54 
55 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
56 {
57 	u32 val;
58 
59 	val = inl(base);
60 	if (value)
61 		val |= (1UL << offset);
62 	else
63 		val &= ~(1UL << offset);
64 	outl(val, base);
65 
66 	return 0;
67 }
68 
69 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
70 {
71 	u32 val;
72 
73 	if (!dir) {
74 		val = inl(base);
75 		val |= (1UL << offset);
76 		outl(val, base);
77 	} else {
78 		val = inl(base);
79 		val &= ~(1UL << offset);
80 		outl(val, base);
81 	}
82 
83 	return 0;
84 }
85 
86 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
87 {
88 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
89 	u32 gpiobase;
90 	int offset;
91 	int ret;
92 
93 	ret = pch_get_gpio_base(dev->parent, &gpiobase);
94 	if (ret)
95 		return ret;
96 
97 	offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
98 	if (offset == -1) {
99 		debug("%s: Invalid register offset %d\n", __func__, offset);
100 		return -EINVAL;
101 	}
102 	plat->offset = offset;
103 	plat->base_addr = gpiobase + offset;
104 	plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
105 				      "bank-name", NULL);
106 
107 	return 0;
108 }
109 
110 static int ich6_gpio_probe(struct udevice *dev)
111 {
112 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
113 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
114 	struct ich6_bank_priv *bank = dev_get_priv(dev);
115 
116 	uc_priv->gpio_count = GPIO_PER_BANK;
117 	uc_priv->bank_name = plat->bank_name;
118 	bank->use_sel = plat->base_addr;
119 	bank->io_sel = plat->base_addr + 4;
120 	bank->lvl = plat->base_addr + 8;
121 
122 	return 0;
123 }
124 
125 static int ich6_gpio_request(struct udevice *dev, unsigned offset,
126 			     const char *label)
127 {
128 	struct ich6_bank_priv *bank = dev_get_priv(dev);
129 	u32 tmplong;
130 
131 	/*
132 	 * Make sure that the GPIO pin we want isn't already in use for some
133 	 * built-in hardware function. We have to check this for every
134 	 * requested pin.
135 	 */
136 	tmplong = inl(bank->use_sel);
137 	if (!(tmplong & (1UL << offset))) {
138 		debug("%s: gpio %d is reserved for internal use\n", __func__,
139 		      offset);
140 		return -EPERM;
141 	}
142 
143 	return 0;
144 }
145 
146 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
147 {
148 	struct ich6_bank_priv *bank = dev_get_priv(dev);
149 
150 	return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
151 }
152 
153 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
154 				       int value)
155 {
156 	int ret;
157 	struct ich6_bank_priv *bank = dev_get_priv(dev);
158 
159 	ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
160 	if (ret)
161 		return ret;
162 
163 	return _ich6_gpio_set_value(bank->lvl, offset, value);
164 }
165 
166 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
167 {
168 	struct ich6_bank_priv *bank = dev_get_priv(dev);
169 	u32 tmplong;
170 	int r;
171 
172 	tmplong = inl(bank->lvl);
173 	r = (tmplong & (1UL << offset)) ? 1 : 0;
174 	return r;
175 }
176 
177 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
178 			       int value)
179 {
180 	struct ich6_bank_priv *bank = dev_get_priv(dev);
181 	return _ich6_gpio_set_value(bank->lvl, offset, value);
182 }
183 
184 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
185 {
186 	struct ich6_bank_priv *bank = dev_get_priv(dev);
187 	u32 mask = 1UL << offset;
188 
189 	if (!(inl(bank->use_sel) & mask))
190 		return GPIOF_FUNC;
191 	if (inl(bank->io_sel) & mask)
192 		return GPIOF_INPUT;
193 	else
194 		return GPIOF_OUTPUT;
195 }
196 
197 static const struct dm_gpio_ops gpio_ich6_ops = {
198 	.request		= ich6_gpio_request,
199 	.direction_input	= ich6_gpio_direction_input,
200 	.direction_output	= ich6_gpio_direction_output,
201 	.get_value		= ich6_gpio_get_value,
202 	.set_value		= ich6_gpio_set_value,
203 	.get_function		= ich6_gpio_get_function,
204 };
205 
206 static const struct udevice_id intel_ich6_gpio_ids[] = {
207 	{ .compatible = "intel,ich6-gpio" },
208 	{ }
209 };
210 
211 U_BOOT_DRIVER(gpio_ich6) = {
212 	.name	= "gpio_ich6",
213 	.id	= UCLASS_GPIO,
214 	.of_match = intel_ich6_gpio_ids,
215 	.ops	= &gpio_ich6_ops,
216 	.ofdata_to_platdata	= gpio_ich6_ofdata_to_platdata,
217 	.probe	= ich6_gpio_probe,
218 	.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
219 	.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
220 };
221